37 lines
834 B
C
37 lines
834 B
C
/*
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* \brief CPU register macros for RiscV
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* \author Stefan Kalkowski
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* \date 2017-09-14
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__RISCV__REGISTER_MACROS_H_
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#define _SRC__LIB__HW__SPEC__RISCV__REGISTER_MACROS_H_
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#include <util/register.h>
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#define RISCV_SUPERVISOR_REGISTER(name, reg, ...) \
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struct name : Genode::Register<64> \
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{ \
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static access_t read() \
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{ \
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access_t v; \
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asm volatile ("csrr %0, " #reg : "=r" (v) :: ); \
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return v; \
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} \
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\
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static void write(access_t const v) { \
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asm volatile ("csrw " #reg ", %0" :: "r" (v) : ); } \
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\
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__VA_ARGS__; \
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};
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#endif /* _SRC__LIB__HW__SPEC__ARM__REGISTER_MACROS_H_ */
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