130 lines
2.7 KiB
C++
130 lines
2.7 KiB
C++
/*
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* \brief L2 outer cache controller ARM PL310
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* \author Johannes Schlatow
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* \author Stefan Kalkowski
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* \author Martin Stein
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* \date 2014-06-02
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*/
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/*
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* Copyright (C) 2014-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__ARM__PL310_H_
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#define _SRC__LIB__HW__SPEC__ARM__PL310_H_
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/* Genode includes */
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#include <util/mmio.h>
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namespace Hw { struct Pl310; }
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class Hw::Pl310 : public Genode::Mmio
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{
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protected:
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struct Control : Register <0x100, 32>
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{
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struct Enable : Bitfield<0,1> { };
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};
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struct Aux : Register<0x104, 32>
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{
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struct Full_line_of_zero : Bitfield<0,1> {};
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struct Associativity : Bitfield<16,1>
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{
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enum { WAY_8, WAY_16 };
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};
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struct Way_size : Bitfield<17,3>
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{
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enum {
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RESERVED,
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KB_16,
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KB_32,
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KB_64,
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KB_128,
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KB_256,
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KB_512
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};
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};
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struct Share_override : Bitfield<22,1> { };
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struct Replacement_policy : Bitfield<25,1>
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{
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enum { ROUND_ROBIN, PRAND };
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};
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struct Ns_lockdown : Bitfield<26,1> { };
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struct Ns_irq_ctrl : Bitfield<27,1> { };
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struct Data_prefetch : Bitfield<28,1> { };
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struct Inst_prefetch : Bitfield<29,1> { };
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struct Early_bresp : Bitfield<30,1> { };
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};
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struct Tag_ram : Register<0x108, 32>
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{
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struct Setup_latency : Bitfield<0,3> { };
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struct Read_latency : Bitfield<4,3> { };
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struct Write_latency : Bitfield<8,3> { };
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};
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struct Data_ram : Register<0x10c, 32>
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{
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struct Setup_latency : Bitfield<0,3> { };
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struct Read_latency : Bitfield<4,3> { };
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struct Write_latency : Bitfield<8,3> { };
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};
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struct Irq_mask : Register <0x214, 32> { };
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struct Irq_clear : Register <0x220, 32> { };
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struct Cache_sync : Register <0x730, 32> { };
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struct Invalidate_by_way : Register <0x77c, 32> { };
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struct Clean_invalidate_by_way : Register <0x7fc, 32> { };
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struct Debug : Register<0xf40, 32>
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{
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struct Dcl : Bitfield<0,1> { };
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struct Dwb : Bitfield<1,1> { };
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};
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struct Prefetch_ctrl : Register<0xf60, 32>
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{
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struct Data_prefetch : Bitfield<28,1> { };
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struct Inst_prefetch : Bitfield<29,1> { };
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};
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void _sync() { while (read<Cache_sync>()) ; }
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public:
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Pl310(Genode::addr_t const base) : Mmio(base) { }
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void enable() {}
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void disable() {}
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void clean_invalidate()
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{
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write<Clean_invalidate_by_way>((1UL << 16) - 1);
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_sync();
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}
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void invalidate()
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{
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write<Invalidate_by_way>((1UL << 16) - 1);
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_sync();
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}
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void mask_interrupts()
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{
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write<Irq_mask>(0);
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write<Irq_clear>(~0UL);
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}
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};
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#endif /* _SRC__LIB__HW__SPEC__ARM__PL310_H_ */
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