119 lines
2.4 KiB
C++
119 lines
2.4 KiB
C++
/*
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* \brief Freescale's TrustZone aware interrupt controller
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* \author Stefan Kalkowski
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_
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#define _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_
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#include <util/mmio.h>
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namespace Hw { class Pic; }
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class Hw::Pic : public Genode::Mmio
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{
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public:
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enum { NR_OF_IRQ = 109, };
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protected:
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/**
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* Software Interrupt Trigger Register
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*/
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struct Swint : Register<0xf00, 32> {
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struct Intid : Bitfield<0,10> { }; };
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/**
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* Interrupt control register
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*/
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struct Intctrl : Register<0, 32>
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{
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struct Enable : Bitfield<0,1> { };
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struct Nsen : Bitfield<16,1> { };
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struct Nsen_mask : Bitfield<31,1> { };
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};
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/**
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* Priority mask register
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*/
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struct Priomask : Register<0xc, 32> {
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struct Mask : Bitfield<0,8> { }; };
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/**
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* Interrupt security registers
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*/
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struct Intsec : Register_array<0x80, 32, NR_OF_IRQ, 1> {
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struct Nonsecure : Bitfield<0, 1> { }; };
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/**
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* Interrupt set enable registers
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*/
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struct Enset : Register_array<0x100, 32, NR_OF_IRQ, 1, true> {
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struct Set_enable : Bitfield<0, 1> { }; };
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/**
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* Interrupt clear enable registers
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*/
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struct Enclear : Register_array<0x180, 32, NR_OF_IRQ, 1, true> {
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struct Clear_enable : Bitfield<0, 1> { }; };
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/**
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* Interrupt priority level registers
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*/
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struct Priority : Register_array<0x400, 32, NR_OF_IRQ, 8> { };
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/**
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* Highest interrupt pending registers
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*/
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struct Hipndr : Register_array<0xd80, 32, NR_OF_IRQ, 1, true> {
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struct Pending : Bitfield<0, 1> { }; };
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/**
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* Validate request number 'i'
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*/
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bool _valid(unsigned const i) const { return i < NR_OF_IRQ; }
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public:
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Pic();
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/**
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* Receive a pending request number 'i'
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*/
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bool take_request(unsigned & i)
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{
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for (unsigned j = 0; j < NR_OF_IRQ; j++) {
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if (!read<Hipndr::Pending>(j)) { continue; }
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i = j;
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return true;
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}
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return false;
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}
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void finish_request() { }
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/**
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* Unmask interrupt 'i'
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*/
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void unmask(unsigned const i, unsigned) {
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if (_valid(i)) { write<Enset::Set_enable>(1, i); } }
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/**
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* Mask interrupt 'i'
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*/
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void mask(unsigned const i) {
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if (_valid(i)) { write<Enclear::Clear_enable>(1, i); } }
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};
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#endif /* _SRC__LIB__HW__SPEC__ARM__IMX_TZIC_H_ */
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