492 lines
12 KiB
C++
492 lines
12 KiB
C++
/*
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* \brief SDHCI controller driver
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* \author Norman Feske
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* \author Christian Helmuth
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* \date 2014-09-21
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*/
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/*
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* Copyright (C) 2014 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _SDHCI_H_
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#define _SDHCI_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <os/attached_ram_dataspace.h>
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#include <irq_session/connection.h>
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#include <drivers/board_base.h>
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/* local includes */
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#include <sd_card.h>
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struct Sdhci : Genode::Mmio
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{
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enum { verbose = false };
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typedef Genode::size_t size_t;
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struct Blksizecnt : Register<0x4, 32>
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{
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struct Blkcnt : Bitfield<16, 16> { };
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struct Blksize : Bitfield<0, 10> { };
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};
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struct Resp0 : Register<0x10, 32> { };
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struct Resp1 : Register<0x14, 32> { };
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struct Resp2 : Register<0x18, 32> { };
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struct Resp3 : Register<0x1c, 32> { };
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struct Data : Register<0x20, 32> { };
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struct Control0 : Register<0x28, 32>
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{
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struct Hctl_dwidth : Bitfield<1, 1> { };
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struct Hctl_hs_en : Bitfield<2, 1> { };
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};
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struct Control1 : Register<0x2c, 32>
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{
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struct Clk_internal_en : Bitfield<0, 1> { };
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struct Clk_internal_stable : Bitfield<1, 1> { };
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struct Clk_en : Bitfield<2, 1> { };
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struct Clk_freq8 : Bitfield<8, 8> { };
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struct Clk_freq_ms2 : Bitfield<6, 2> { };
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struct Data_tounit : Bitfield<16, 4> { };
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struct Srst_hc : Bitfield<24, 1> { };
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struct Srst_cmd : Bitfield<25, 1> { };
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struct Srst_data : Bitfield<26, 1> { };
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};
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struct Status : Register<0x24, 32>
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{
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struct Inhibit : Bitfield<0, 2> { };
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struct Bwe : Bitfield<10, 1> { };
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struct Bre : Bitfield<11, 1> { };
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};
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struct Arg1 : Register<0x8, 32> { };
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struct Cmdtm : Register<0xc, 32>
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{
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struct Index : Bitfield<24, 6> { };
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struct Isdata : Bitfield<21, 1> { };
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struct Tm_blkcnt_en : Bitfield<1, 1> { };
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struct Tm_multi_block : Bitfield<5, 1> { };
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struct Tm_auto_cmd_en : Bitfield<2, 2>
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{
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enum { CMD12 = 1 };
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};
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struct Tm_dat_dir : Bitfield<4, 1>
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{
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enum { WRITE = 0, READ = 1 };
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};
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struct Rsp_type : Bitfield<16, 2>
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{
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enum Response { RESPONSE_NONE = 0,
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RESPONSE_136_BIT = 1,
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RESPONSE_48_BIT = 2,
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RESPONSE_48_BIT_WITH_BUSY = 3 };
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};
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};
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struct Interrupt : Register<0x30, 32>
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{
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struct Cmd_done : Bitfield<0, 1> { };
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struct Data_done : Bitfield<1, 1> { };
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};
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struct Irpt_mask : Register<0x34, 32> { };
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struct Irpt_en : Register<0x38, 32> { };
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Sdhci(Genode::addr_t const mmio_base) : Genode::Mmio(mmio_base) { }
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};
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struct Sdhci_controller : private Sdhci, public Sd_card::Host_controller
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{
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private:
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Delayer &_delayer;
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Sd_card::Card_info _card_info;
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Genode::Irq_connection _irq;
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void _set_and_enable_clock(unsigned divider)
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{
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Control1::access_t v = read<Control1>();
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Control1::Clk_freq8::set(v, divider);
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Control1::Clk_freq_ms2::set(v, 0);
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Control1::Clk_internal_en::set(v, 1);
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write<Control1>(v);
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if (!wait_for<Control1::Clk_internal_stable>(1, _delayer)) {
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PERR("could not set internal clock");
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throw Detection_failed();
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}
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write<Control1::Clk_en>(1);
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_delayer.usleep(10*1000);
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/* data timeout unit exponent */
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write<Control1::Data_tounit>(0xe);
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}
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Sd_card::Card_info _init()
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{
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using namespace Sd_card;
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/* reset host controller */
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{
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Control1::access_t v = read<Control1>();
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Control1::Srst_hc::set(v);
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Control1::Srst_data::set(v);
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write<Control1>(v);
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}
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if (!wait_for<Control1::Srst_hc>(0, _delayer)) {
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PERR("host-controller soft reset timed out");
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throw Detection_failed();
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}
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/* enable interrupt status reporting */
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write<Irpt_mask>(~0UL);
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write<Irpt_en>(~0UL);
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/*
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* We don't read the capability register as the BCM2835 always
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* returns all bits set to zero.
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*/
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_set_and_enable_clock(240);
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if (!issue_command(Go_idle_state())) {
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PWRN("Go_idle_state command failed");
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throw Detection_failed();
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}
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_delayer.usleep(2000);
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if (!issue_command(Send_if_cond())) {
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PWRN("Send_if_cond command failed");
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throw Detection_failed();
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}
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if (read<Resp0>() != 0x1aa) {
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PERR("unexpected response of Send_if_cond command");
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throw Detection_failed();
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}
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/*
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* We need to issue the same Sd_send_op_cond command multiple
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* times. The first time, we receive the status information. On
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* subsequent attempts, the response tells us that the card is
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* busy. Usually, the command is issued twice. We give up if the
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* card is not reaching busy state after one second.
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*/
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int i = 1000;
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for (; i > 0; --i) {
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if (!issue_command(Sd_send_op_cond(0x18000, true))) {
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PWRN("Sd_send_op_cond command failed");
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throw Detection_failed();
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}
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if (Sd_card::Ocr::Busy::get(read<Resp0>()))
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break;
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_delayer.usleep(1000);
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}
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if (i == 0) {
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PERR("Sd_send_op_cond timed out, could no power-on SD card");
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throw Detection_failed();
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}
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Card_info card_info = _detect();
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/*
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* Switch card to use 4 data signals
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*/
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if (!issue_command(Set_bus_width(Set_bus_width::Arg::Bus_width::FOUR_BITS),
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card_info.rca())) {
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PWRN("Set_bus_width(FOUR_BITS) command failed");
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throw Detection_failed();
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}
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/* switch host controller to use 4 data signals */
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{
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Control0::access_t v = read<Control0>();
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Control0::Hctl_dwidth::set(v);
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Control0::Hctl_hs_en::set(v);
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write<Control0>(v);
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}
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_delayer.usleep(10*1000);
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/*
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* Accelerate clock, the divider is hard-coded for now.
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*
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* The Raspberry Pi report as clock of 250 MHz. According to the
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* SDHCI specification, it is possible to driver SD cards with
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* 50 MHz in high-speed mode (Hctl_hs_en).
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*/
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_set_and_enable_clock(5);
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return card_info;
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}
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/**
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* Define the block count for the next data transfer
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*/
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void _set_block_count(size_t block_count)
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{
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/*
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* The 'Blksizecnt' register must be written in one step. If we
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* used subsequent writes for the 'Blkcnt' and 'Blksize' bitfields,
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* the host controller of the BCM2835 would fail to recognize any
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* but the first write operation.
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*/
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Blksizecnt::access_t v = read<Blksizecnt>();
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Blksizecnt::Blkcnt::set(v, block_count);
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Blksizecnt::Blksize::set(v, 0x200);
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write<Blksizecnt>(v);
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}
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template <typename REG>
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bool _poll_and_wait_for(unsigned value)
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{
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/* poll for a while */
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if (wait_for<REG>(value, _delayer, 5000, 0))
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return true;
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/* if the value were not reached while polling, start sleeping */
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return wait_for<REG>(value, _delayer);
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}
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public:
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/**
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* Constructor
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*
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* \param mmio_base local base address of MMIO registers
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*/
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Sdhci_controller(Genode::addr_t const mmio_base, Delayer &delayer,
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unsigned irq, bool use_dma)
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:
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Sdhci(mmio_base), _delayer(delayer), _card_info(_init()), _irq(irq)
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{ }
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/****************************************
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** Sd_card::Host_controller interface **
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****************************************/
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bool _issue_command(Sd_card::Command_base const &command)
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{
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if (verbose)
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PLOG("-> index=0x%08x, arg=0x%08x, rsp_type=%d",
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command.index, command.arg, command.rsp_type);
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if (!_poll_and_wait_for<Status::Inhibit>(0)) {
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PERR("controller inhibits issueing commands");
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return false;
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}
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/* write command argument */
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write<Arg1>(command.arg);
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/* assemble command register */
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Cmdtm::access_t cmd = 0;
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Cmdtm::Index::set(cmd, command.index);
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if (command.transfer != Sd_card::TRANSFER_NONE) {
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Cmdtm::Isdata::set(cmd);
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Cmdtm::Tm_blkcnt_en::set(cmd);
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Cmdtm::Tm_multi_block::set(cmd);
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if (command.index == Sd_card::Read_multiple_block::INDEX
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|| command.index == Sd_card::Write_multiple_block::INDEX) {
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Cmdtm::Tm_auto_cmd_en::set(cmd, Cmdtm::Tm_auto_cmd_en::CMD12);
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}
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/* set data-direction bit depending on the command */
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bool const read = command.transfer == Sd_card::TRANSFER_READ;
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Cmdtm::Tm_dat_dir::set(cmd, read ? Cmdtm::Tm_dat_dir::READ
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: Cmdtm::Tm_dat_dir::WRITE);
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}
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Cmdtm::access_t rsp_type = 0;
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switch (command.rsp_type) {
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case Sd_card::RESPONSE_NONE: rsp_type = Cmdtm::Rsp_type::RESPONSE_NONE; break;
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case Sd_card::RESPONSE_136_BIT: rsp_type = Cmdtm::Rsp_type::RESPONSE_136_BIT; break;
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case Sd_card::RESPONSE_48_BIT: rsp_type = Cmdtm::Rsp_type::RESPONSE_48_BIT; break;
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case Sd_card::RESPONSE_48_BIT_WITH_BUSY: rsp_type = Cmdtm::Rsp_type::RESPONSE_48_BIT_WITH_BUSY; break;
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}
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Cmdtm::Rsp_type::set(cmd, rsp_type);
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/* write command */
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write<Cmdtm>(cmd);
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if (!_poll_and_wait_for<Interrupt::Cmd_done>(1)) {
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PERR("command timed out");
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return false;
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}
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/* clear interrupt state */
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write<Interrupt::Cmd_done>(1);
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return true;
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}
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Sd_card::Card_info card_info() const
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{
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return _card_info;
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}
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Sd_card::Cid _read_cid()
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{
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Sd_card::Cid cid;
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cid.raw_0 = read<Resp0>();
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cid.raw_1 = read<Resp1>();
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cid.raw_2 = read<Resp2>();
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cid.raw_3 = read<Resp3>();
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return cid;
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}
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Sd_card::Csd _read_csd()
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{
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Sd_card::Csd csd;
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csd.csd0 = read<Resp0>();
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csd.csd1 = read<Resp1>();
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csd.csd2 = read<Resp2>();
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csd.csd3 = read<Resp3>();
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return csd;
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}
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unsigned _read_rca()
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{
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return Sd_card::Send_relative_addr::Response::Rca::get(read<Resp0>());
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}
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/**
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* Read data blocks from SD card
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*
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* \return true on success
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*/
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bool read_blocks(size_t block_number, size_t block_count, char *out_buffer)
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{
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using namespace Sd_card;
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_set_block_count(block_count);
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if (!issue_command(Read_multiple_block(block_number))) {
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PERR("Read_multiple_block failed, Status: 0x%08x", read<Status>());
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return false;
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}
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Data::access_t *dst = (Data::access_t *)(out_buffer);
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for (size_t i = 0; i < block_count; i++) {
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/*
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* Check for buffer-read enable bit for each block
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*
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* According to the BCM2835 documentation, this bit is
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* reserved but it actually corresponds to the bre status
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* bit as described in the SDHCI specification.
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*/
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if (!_poll_and_wait_for<Status::Bre>(1))
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return false;
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/* read data from sdhci buffer */
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for (size_t j = 0; j < 512/sizeof(Data::access_t); j++)
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*dst++ = read<Data>();
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}
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if (!_poll_and_wait_for<Interrupt::Data_done>(1)) {
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PERR("completion of read request failed (interrupt status %08x)",
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read<Interrupt>());
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return false;
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}
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/* clear interrupt state */
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write<Interrupt::Data_done>(1);
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return true;
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}
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/**
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* Write data blocks to SD card
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*
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* \return true on success
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*/
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bool write_blocks(size_t block_number, size_t block_count, char const *buffer)
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{
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using namespace Sd_card;
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_set_block_count(block_count);
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if (!issue_command(Write_multiple_block(block_number))) {
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PERR("Write_multiple_block failed, Status: 0x%08x", read<Status>());
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return false;
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}
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Data::access_t const *src = (Data::access_t const *)(buffer);
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for (size_t i = 0; i < block_count; i++) {
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/* check for buffer-write enable bit for each block */
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if (!_poll_and_wait_for<Status::Bwe>(1))
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return false;
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/* write data into sdhci buffer */
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for (size_t j = 0; j < 512/sizeof(Data::access_t); j++)
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write<Data>(*src++);
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}
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if (!_poll_and_wait_for<Interrupt::Data_done>(1)) {
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PERR("completion of write request failed (interrupt status %08x)",
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read<Interrupt>());
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return false;
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}
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/* clear interrupt state */
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write<Interrupt::Data_done>(1);
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return true;
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}
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/**
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* Read data blocks from SD card via master DMA
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*
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* \return true on success
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*/
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bool read_blocks_dma(size_t block_number, size_t block_count,
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Genode::addr_t out_buffer_phys)
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{
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return false;
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}
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/**
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* Write data blocks to SD card via master DMA
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*
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* \return true on success
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*/
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bool write_blocks_dma(size_t block_number, size_t block_count,
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Genode::addr_t buffer_phys)
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{
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using namespace Sd_card;
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return false;
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}
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};
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#endif /* _SDHCI_H_ */
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