209 lines
6.6 KiB
C++
209 lines
6.6 KiB
C++
/*
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* \brief Driver for the CoreLink Trustzone Address Space Controller TSC-380
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* \author Stefan Kalkowski
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* \date 2012-07-04
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE_HW__SRC__SERVER__VMM__TSC_380_H_
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#define _BASE_HW__SRC__SERVER__VMM__TSC_380_H_
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/* Genode includes */
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#include <util/mmio.h>
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class Tsc_380 : Genode::Mmio
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{
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private:
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enum {
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REGION0_REG_OFF = 0x100,
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REGION1_REG_OFF = 0x110,
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REGION2_REG_OFF = 0x120,
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REGION3_REG_OFF = 0x130,
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REGION4_REG_OFF = 0x140,
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REGION5_REG_OFF = 0x150,
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REGION6_REG_OFF = 0x160,
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REGION7_REG_OFF = 0x170,
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REGION8_REG_OFF = 0x180,
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REGION9_REG_OFF = 0x190,
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REGION10_REG_OFF = 0x1a0,
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REGION11_REG_OFF = 0x1b0,
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REGION12_REG_OFF = 0x1c0,
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REGION13_REG_OFF = 0x1d0,
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REGION14_REG_OFF = 0x1e0,
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REGION15_REG_OFF = 0x1f0,
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REGION_LOW_OFF = 0x0,
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REGION_HIGH_OFF = 0x4,
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REGION_ATTR_OFF = 0x8,
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};
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/**
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* Configuration register
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*/
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struct Config : public Register<0, 32>
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{
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struct Region_number : Bitfield<0,4> { };
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struct Address_width : Bitfield<8,6> { };
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};
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struct Irq_status : public Register<0x10, 32>
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{
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struct Status : Bitfield<0,1> {};
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struct Overrun : Bitfield<1,1> {};
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};
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struct Irq_clear : public Register<0x14, 32>
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{
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struct Status : Bitfield<0,1> {};
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struct Overrun : Bitfield<1,1> {};
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};
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/**
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* Fail address low register
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*/
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struct Fail_low : public Register<0x20, 32> { };
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template <Genode::off_t OFF>
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struct Region_low : public Register<OFF + REGION_LOW_OFF, 32>
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{
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enum { MASK = ~0UL << 15 };
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};
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template <Genode::off_t OFF>
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struct Region_high : public Register<OFF + REGION_HIGH_OFF, 32> { };
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template <Genode::off_t OFF>
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struct Region_attr : public Register<OFF + REGION_ATTR_OFF, 32>
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{
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struct Enable :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<0, 1> { };
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struct Size :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<1, 6>
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{
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enum {
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SZ_32K = 14,
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SZ_64K,
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SZ_128K,
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SZ_256K,
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SZ_512K,
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SZ_1M,
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SZ_2M,
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SZ_4M,
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SZ_8M,
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SZ_16M,
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SZ_32M,
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SZ_64M,
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SZ_128M,
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SZ_256M,
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SZ_512M,
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SZ_1G,
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};
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};
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struct Subreg0 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<8, 1> { };
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struct Subreg1 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<9, 1> { };
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struct Subreg2 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<10, 1> { };
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struct Subreg3 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<11, 1> { };
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struct Subreg4 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<12, 1> { };
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struct Subreg5 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<13, 1> { };
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struct Subreg6 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<14, 1> { };
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struct Subreg7 :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<15, 1> { };
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struct Normal_write :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<28, 1> { };
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struct Normal_read :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<29, 1> { };
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struct Secure_write :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<30, 1> { };
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struct Secure_read :
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Register<OFF + REGION_ATTR_OFF, 32>::template Bitfield<31, 1> { };
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};
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typedef Region_low<0x100> Region0_low;
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public:
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Tsc_380(Genode::addr_t const base) : Genode::Mmio(base)
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{
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/* Access to AACI, MMCI, KMI0/1 */
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write<Region_low<REGION15_REG_OFF> >(0x10000000);
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write<Region_high<REGION15_REG_OFF> >(0x10008000);
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write<Region_attr<REGION15_REG_OFF>::Enable>(1);
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write<Region_attr<REGION15_REG_OFF>::Size>(Region_attr<REGION15_REG_OFF>::Size::SZ_32K);
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write<Region_attr<REGION15_REG_OFF>::Normal_read>(1);
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write<Region_attr<REGION15_REG_OFF>::Normal_write>(1);
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write<Region_attr<REGION15_REG_OFF>::Secure_read>(1);
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write<Region_attr<REGION15_REG_OFF>::Secure_write>(1);
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write<Region_attr<REGION15_REG_OFF>::Subreg0>(1);
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write<Region_attr<REGION15_REG_OFF>::Subreg1>(1);
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write<Region_attr<REGION15_REG_OFF>::Subreg2>(1);
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write<Region_attr<REGION15_REG_OFF>::Subreg3>(1);
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/* Access to UART0, and WDT */
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write<Region_low<REGION14_REG_OFF> >(0x10008000);
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write<Region_high<REGION14_REG_OFF> >(0x10010000);
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write<Region_attr<REGION14_REG_OFF>::Enable>(1);
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write<Region_attr<REGION14_REG_OFF>::Size>(Region_attr<REGION14_REG_OFF>::Size::SZ_32K);
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write<Region_attr<REGION14_REG_OFF>::Normal_read>(1);
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write<Region_attr<REGION14_REG_OFF>::Normal_write>(1);
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write<Region_attr<REGION14_REG_OFF>::Secure_read>(1);
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write<Region_attr<REGION14_REG_OFF>::Secure_write>(1);
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write<Region_attr<REGION14_REG_OFF>::Subreg0>(1);
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write<Region_attr<REGION14_REG_OFF>::Subreg2>(1);
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write<Region_attr<REGION14_REG_OFF>::Subreg3>(1);
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write<Region_attr<REGION14_REG_OFF>::Subreg4>(1);
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write<Region_attr<REGION14_REG_OFF>::Subreg5>(1);
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write<Region_attr<REGION14_REG_OFF>::Subreg6>(1);
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/* Access to SP804 2/3, and RTC */
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write<Region_low<REGION13_REG_OFF> >(0x10010000);
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write<Region_high<REGION13_REG_OFF> >(0x10018000);
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write<Region_attr<REGION13_REG_OFF>::Enable>(1);
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write<Region_attr<REGION13_REG_OFF>::Size>(Region_attr<REGION13_REG_OFF>::Size::SZ_32K);
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write<Region_attr<REGION13_REG_OFF>::Normal_read>(1);
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write<Region_attr<REGION13_REG_OFF>::Normal_write>(1);
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write<Region_attr<REGION13_REG_OFF>::Secure_read>(1);
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write<Region_attr<REGION13_REG_OFF>::Secure_write>(1);
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write<Region_attr<REGION13_REG_OFF>::Subreg0>(1);
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write<Region_attr<REGION13_REG_OFF>::Subreg1>(1);
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write<Region_attr<REGION13_REG_OFF>::Subreg3>(1);
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write<Region_attr<REGION13_REG_OFF>::Subreg4>(1);
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write<Region_attr<REGION13_REG_OFF>::Subreg5>(1);
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write<Region_attr<REGION13_REG_OFF>::Subreg6>(1);
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/* Access to Ethernet and USB */
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write<Region_low<REGION12_REG_OFF> >(0x4e000000);
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write<Region_high<REGION12_REG_OFF> >(0x50000000);
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write<Region_attr<REGION12_REG_OFF>::Enable>(1);
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write<Region_attr<REGION12_REG_OFF>::Size>(Region_attr<REGION12_REG_OFF>::Size::SZ_32M);
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write<Region_attr<REGION12_REG_OFF>::Normal_read>(1);
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write<Region_attr<REGION12_REG_OFF>::Normal_write>(1);
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write<Region_attr<REGION12_REG_OFF>::Secure_read>(1);
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write<Region_attr<REGION12_REG_OFF>::Secure_write>(1);
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/* clear interrupts */
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write<Irq_clear>(0x3);
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}
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void* last_failed_access() {
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void *ret = (void*) read<Fail_low>();
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write<Irq_clear>(0x3);
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return ret;
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}
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};
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#endif /* _BASE_HW__SRC__SERVER__VMM__TSC_380_H_ */
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