101 lines
2.7 KiB
C++
101 lines
2.7 KiB
C++
/*
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* \brief Driver for the Motherboard Express system registers
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* \author Stefan Kalkowski
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* \date 2012-09-21
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE_HW__SRC__SERVER__VMM__SYS_REG_H_
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#define _BASE_HW__SRC__SERVER__VMM__SYS_REG_H_
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/* Genode includes */
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#include <util/mmio.h>
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class Sys_reg : Genode::Mmio
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{
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private:
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struct Sys_mci : public Register<0x48, 32> {};
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struct Sys_24mhz : public Register<0x5c, 32> {};
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struct Sys_misc : public Register<0x60, 32> {};
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struct Sys_cfg_data : public Register<0xa0, 32, true> {};
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struct Sys_cfg_ctrl : public Register<0xa4, 32, true>
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{
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struct Device : Bitfield<0,12> { };
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struct Position : Bitfield<12,4> { };
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struct Site : Bitfield<16,2> { };
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struct Function : Bitfield<20,6> { };
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struct Write : Bitfield<30,1> { };
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struct Start : Bitfield<31,1> { };
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};
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struct Sys_cfg_stat : public Register<0xa8, 32>
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{
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struct Complete : Bitfield<0,1> { };
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struct Error : Bitfield<1,1> { };
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};
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public:
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Sys_reg(Genode::addr_t const base) : Genode::Mmio(base) {}
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Genode::uint32_t counter() { return read<Sys_24mhz>(); }
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Genode::uint32_t misc_flags() { return read<Sys_misc>(); }
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void osc1(Genode::uint32_t mhz)
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{
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write<Sys_cfg_stat::Complete>(0);
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write<Sys_cfg_data>(mhz);
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write<Sys_cfg_ctrl>(Sys_cfg_ctrl::Device::bits(1) |
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Sys_cfg_ctrl::Site::bits(1) |
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Sys_cfg_ctrl::Function::bits(1) |
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Sys_cfg_ctrl::Write::bits(1) |
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Sys_cfg_ctrl::Start::bits(1));
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while (!read<Sys_cfg_stat::Complete>()) ;
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}
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void dvi_source(Genode::uint32_t site)
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{
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if (site > 2) {
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PERR("Invalid site value %u ignored", site);
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return;
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}
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write<Sys_cfg_stat::Complete>(0);
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write<Sys_cfg_data>(site);
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write<Sys_cfg_ctrl>(Sys_cfg_ctrl::Site::bits(1) |
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Sys_cfg_ctrl::Function::bits(0x7) |
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Sys_cfg_ctrl::Write::bits(1) |
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Sys_cfg_ctrl::Start::bits(1));
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while (!read<Sys_cfg_stat::Complete>()) ;
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}
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void dvi_mode(Genode::uint32_t mode)
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{
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if (mode > 4) {
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PERR("Invalid dvi mode %u ignored", mode);
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return;
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}
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write<Sys_cfg_stat::Complete>(0);
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write<Sys_cfg_data>(mode);
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write<Sys_cfg_ctrl>(Sys_cfg_ctrl::Function::bits(0xb) |
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Sys_cfg_ctrl::Write::bits(1) |
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Sys_cfg_ctrl::Start::bits(1));
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while (!read<Sys_cfg_stat::Complete>()) ;
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}
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Genode::uint32_t mci_status() { return read<Sys_mci>(); }
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};
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#endif /* _BASE_HW__SRC__SERVER__VMM__SYS_REG_H_ */
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