127 lines
4.2 KiB
C++
127 lines
4.2 KiB
C++
/*
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* \brief Driver for the Trustzone Protection Controller BP147
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* \author Stefan Kalkowski
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* \date 2012-07-04
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _BASE_HW__SRC__SERVER__VMM__BP_147_H_
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#define _BASE_HW__SRC__SERVER__VMM__BP_147_H_
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/* Genode includes */
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#include <util/mmio.h>
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class Bp_147 : Genode::Mmio
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{
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private:
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/**
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* Secure RAM Region Size Register
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*/
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struct Tzpcr0size : public Register<0x00, 32>
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{
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struct R0size : Bitfield<0,10> { };
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};
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/**
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* Decode Protection 0 Registers
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*/
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template <Genode::off_t OFF>
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struct Tzpcdecprot0 : public Register<OFF, 32>
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{
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struct Pl341_apb : Register<OFF, 32>::template Bitfield<0,1> {};
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struct Pl354_apb : Register<OFF, 32>::template Bitfield<1,1> {};
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struct Scc : Register<OFF, 32>::template Bitfield<2,1> {};
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struct Dual_timer : Register<OFF, 32>::template Bitfield<4,1> {};
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struct Watchdog : Register<OFF, 32>::template Bitfield<5,1> {};
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struct Tzpc : Register<OFF, 32>::template Bitfield<6,1> {};
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struct Pl351_apb : Register<OFF, 32>::template Bitfield<7,1> {};
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struct Fast_pl301_apb : Register<OFF, 32>::template Bitfield<9,1> {};
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struct Slow_pl301_apb : Register<OFF, 32>::template Bitfield<10,1> {};
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struct Dmc_tzasc : Register<OFF, 32>::template Bitfield<12,1> {};
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struct Nmc_tzasc : Register<OFF, 32>::template Bitfield<12,1> {};
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struct Smc_tzasc : Register<OFF, 32>::template Bitfield<13,1> {};
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struct Debug_apb_phs : Register<OFF, 32>::template Bitfield<14,1> {};
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};
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/**
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* Decode Protection 1 Registers
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*/
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template <Genode::off_t OFF>
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struct Tzpcdecprot1 : public Register<OFF, 32>
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{
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struct External_axi_slave_port
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: Register<OFF, 32>::template Bitfield<0,1> {};
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/* SMC access */
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struct Pl354_axi
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: Register<OFF, 32>::template Bitfield<1,1> {};
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struct Pl351_axi
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: Register<OFF, 32>::template Bitfield<2,1> {};
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struct Entire_apb
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: Register<OFF, 32>::template Bitfield<3,1> {};
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struct Pl111_configuration_port
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: Register<OFF, 32>::template Bitfield<4,1> {};
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struct Axi_ram
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: Register<OFF, 32>::template Bitfield<5,1> {};
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/* DDR RAM access */
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struct Pl341_axi
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: Register<OFF, 32>::template Bitfield<6,1> {};
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/* ACP access */
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struct Cortexa9_coherency_port
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: Register<OFF, 32>::template Bitfield<8,1> {};
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struct Entire_slow_axi_system
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: Register<OFF, 32>::template Bitfield<9,1> {};
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};
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/**
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* Decode Protection 2 Registers
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*/
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template <Genode::off_t OFF>
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struct Tzpcdecprot2 : public Register<OFF, 32>
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{
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struct External_master_tz : Register<OFF, 32>::template Bitfield<0,1> {};
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struct Dap_tz_override : Register<OFF, 32>::template Bitfield<1,1> {};
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struct Pl111_master_tz : Register<OFF, 32>::template Bitfield<2,1> {};
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struct Dmc_tzasc_lockdown : Register<OFF, 32>::template Bitfield<3,1> {};
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struct Nmc_tzasc_lockdown : Register<OFF, 32>::template Bitfield<4,1> {};
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struct Smc_tzasc_lockdown : Register<OFF, 32>::template Bitfield<5,1> {};
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};
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struct Tzpcdecprot0stat : Tzpcdecprot0<0x800> {};
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struct Tzpcdecprot0set : Tzpcdecprot0<0x804> {};
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struct Tzpcdecprot0clr : Tzpcdecprot0<0x808> {};
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struct Tzpcdecprot1stat : Tzpcdecprot1<0x80c> {};
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struct Tzpcdecprot1set : Tzpcdecprot1<0x810> {};
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struct Tzpcdecprot1clr : Tzpcdecprot1<0x814> {};
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struct Tzpcdecprot2stat : Tzpcdecprot2<0x818> {};
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struct Tzpcdecprot2set : Tzpcdecprot2<0x81c> {};
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struct Tzpcdecprot2clr : Tzpcdecprot2<0x820> {};
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public:
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Bp_147(Genode::addr_t const base) : Genode::Mmio(base)
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{
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/**
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* Configure TZPC to allow non-secure AXI signals to
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* Static Memory Controller (SMC),
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* Dynamic Memory Controller (DMC),
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* Accelerator Coherency Port (ACP), and
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* PL111 configuration registers
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*/
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write<Tzpcdecprot1set>(
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Tzpcdecprot1set::Pl341_axi::bits(1) |
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Tzpcdecprot1set::Pl354_axi::bits(1) |
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Tzpcdecprot1set::Cortexa9_coherency_port::bits(1) |
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Tzpcdecprot1set::Pl111_configuration_port::bits(1));
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}
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};
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#endif /* _BASE_HW__SRC__SERVER__VMM__BP_147_H_ */
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