'Core_tlb' ensures that core never throws pagefaults, in contrast to its base 'Tlb' that is planned to use displacement in the future. 'Core_tlb' enables the application of differenet memory attributes in core, according to the board specific partitioning of the physical address space. This way it enables caching in core.
63 lines
1.3 KiB
C++
63 lines
1.3 KiB
C++
/*
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* \brief SW controls for the translation lookaside-buffer
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* \author Martin Stein
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* \date 2012-04-23
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _SRC__CORE__VEA9X4__TLB_H_
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#define _SRC__CORE__VEA9X4__TLB_H_
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/* Genode includes */
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#include <drivers/board.h>
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/* core includes */
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#include <arm/v7/section_table.h>
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/**
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* Software TLB-controls
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*/
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class Tlb : public Arm_v7::Section_table
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{
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public:
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/**
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* Placement new
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*/
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void * operator new (Genode::size_t, void * p) { return p; }
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};
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/**
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* TLB of core
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*
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* Must ensure that core never gets a pagefault.
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*/
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class Core_tlb : public Tlb
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{
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public:
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Core_tlb()
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{
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using namespace Genode;
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/* map RAM */
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translate_dpm_off(Board::RAM_0_BASE, Board::RAM_0_SIZE, 0, 1);
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translate_dpm_off(Board::RAM_1_BASE, Board::RAM_1_SIZE, 0, 1);
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translate_dpm_off(Board::RAM_2_BASE, Board::RAM_2_SIZE, 0, 1);
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translate_dpm_off(Board::RAM_3_BASE, Board::RAM_3_SIZE, 0, 1);
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/* map MMIO */
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translate_dpm_off(Board::MMIO_0_BASE, Board::MMIO_0_SIZE, 1, 0);
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translate_dpm_off(Board::MMIO_1_BASE, Board::MMIO_1_SIZE, 1, 0);
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}
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};
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#endif /* _SRC__CORE__VEA9X4__TLB_H_ */
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