8d03312528
'Core_tlb' ensures that core never throws pagefaults, in contrast to its base 'Tlb' that is planned to use displacement in the future. 'Core_tlb' enables the application of differenet memory attributes in core, according to the board specific partitioning of the physical address space. This way it enables caching in core.
84 lines
1.9 KiB
C++
84 lines
1.9 KiB
C++
/*
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* \brief Parts of platform that are specific to PBXA9
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* \author Martin Stein
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* \date 2012-04-27
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* Genode includes */
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#include <drivers/board.h>
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/* core includes */
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#include <platform.h>
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#include <cortex_a9/cpu.h>
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#include <cortex_a9/no_trustzone/pic.h>
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using namespace Genode;
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Native_region * Platform::_ram_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
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{ Board::RAM_1_BASE, Board::RAM_1_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_irq_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ 0, Cortex_a9_no_trustzone::Pic::MAX_INTERRUPT_ID + 1 }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_irq_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/* core timer */
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{ Cortex_a9::Cpu::PRIVATE_TIMER_IRQ, 1 },
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/* core UART */
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{ Board::PL011_0_IRQ, 1 }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
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{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/* core timer and PIC */
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{ Board::CORTEX_A9_PRIVATE_MEM_BASE, Board::CORTEX_A9_PRIVATE_MEM_SIZE },
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/* core UART */
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{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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