8d03312528
'Core_tlb' ensures that core never throws pagefaults, in contrast to its base 'Tlb' that is planned to use displacement in the future. 'Core_tlb' enables the application of differenet memory attributes in core, according to the board specific partitioning of the physical address space. This way it enables caching in core.
109 lines
2.8 KiB
C++
109 lines
2.8 KiB
C++
/*
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* \brief Driver for ARMv6 section tables
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* \author Martin Stein
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* \date 2012-02-22
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__ARM_V6__SECTION_TABLE_H_
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#define _INCLUDE__ARM_V6__SECTION_TABLE_H_
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/* core includes */
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#include <arm/section_table.h>
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namespace Arm_v6
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{
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using namespace Genode;
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/**
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* First level translation table
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*/
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class Section_table : public Arm::Section_table
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{
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public:
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/**
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* Link to second level translation-table
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*/
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struct Page_table_descriptor : Arm::Section_table::Page_table_descriptor
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{
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/**
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* Compose descriptor value
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*/
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static access_t create(Arm::Page_table * const pt,
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Section_table *)
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{
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return Arm::Section_table::Page_table_descriptor::create(pt);
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}
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};
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/**
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* Section translation descriptor
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*/
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struct Section : Arm::Section_table::Section
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{
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struct P : Bitfield<9, 1> { }; /* enable ECC */
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/**
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* Compose descriptor value
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*/
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static access_t create(bool const w, bool const x,
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bool const k, bool const g,
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bool const d, bool const c,
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addr_t const pa,
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Section_table *)
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{
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return Arm::Section_table::Section::create(w, x, k, g,
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d, c, pa) |
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P::bits(0);
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}
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};
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/**
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* Insert one atomic translation into this table
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*
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* For details see 'Arm::Section_table::insert_translation'
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*/
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unsigned long insert_translation(addr_t const vo, addr_t const pa,
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unsigned long const size_log2,
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bool const w, bool const x,
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bool const k, bool const g,
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bool const d, bool const c,
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void * const extra_space = 0)
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{
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return Arm::Section_table::
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insert_translation<Section_table>(vo, pa, size_log2, w,
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x, k, g, d, c, this,
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extra_space);
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}
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/**
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* Insert translations for given area, do not permit displacement
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*
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* \param vo virtual offset within this table
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* \param s area size
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* \param d wether area maps device IO memory
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* \param c wether area maps cacheable memory
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*/
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void translate_dpm_off(addr_t vo, size_t s,
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bool const d, bool const c)
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{
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Arm::Section_table::
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translate_dpm_off<Section_table>(vo, s, d, c, this);
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}
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};
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}
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bool Arm::cache_support() { return 0; }
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#endif /* _INCLUDE__ARM_V6__SECTION_TABLE_H_ */
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