5c7436bf10
Whether an SoC has the multiprocessing extensions can be read out from the identification registers, and does not need to be specified in each board header. Ref #3445
96 lines
2.6 KiB
C++
96 lines
2.6 KiB
C++
/*
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* \brief Platform implementations specific for base-hw and Raspberry Pi
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* \author Norman Feske
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* \author Stefan Kalkowski
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* \date 2013-04-05
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <hw/assert.h>
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#include <platform.h>
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using namespace Rpi;
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/**
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* Leave out the first page (being 0x0) from bootstraps RAM allocator,
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* some code does not feel happy with addresses being zero
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*/
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Bootstrap::Platform::Board::Board()
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: early_ram_regions(Memory_region { RAM_0_BASE + 0x1000,
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RAM_0_SIZE - 0x1000 }),
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late_ram_regions(Memory_region { RAM_0_BASE, 0x1000 }),
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core_mmio(Memory_region { PL011_0_MMIO_BASE,
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PL011_0_MMIO_SIZE },
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Memory_region { SYSTEM_TIMER_MMIO_BASE,
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SYSTEM_TIMER_MMIO_SIZE },
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Memory_region { IRQ_CONTROLLER_BASE,
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IRQ_CONTROLLER_SIZE },
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Memory_region { USB_DWC_OTG_BASE,
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USB_DWC_OTG_SIZE }) {}
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unsigned Bootstrap::Platform::enable_mmu()
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{
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using ::Board::Cpu;
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struct Sctlr : Cpu::Sctlr
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{
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struct W : Bitfield<3,1> { }; /* enable write buffer */
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struct Dt : Bitfield<16,1> { }; /* global data TCM enable */
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struct It : Bitfield<18,1> { }; /* global instruction TCM enable */
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struct U : Bitfield<22,1> { }; /* enable unaligned data access */
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struct Xp : Bitfield<23,1> { }; /* disable subpage AP bits */
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};
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Cpu::Sctlr::init();
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Cpu::Sctlr::access_t sctlr = Cpu::Sctlr::read();
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Sctlr::W::set(sctlr, 1);
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Sctlr::Dt::set(sctlr, 1);
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Sctlr::It::set(sctlr, 1);
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Sctlr::U::set(sctlr, 1);
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Sctlr::Xp::set(sctlr, 1);
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Cpu::Sctlr::write(sctlr);
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Cpu::Cpsr::init();
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struct Ctr : Cpu::Ctr {
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struct P : Bitfield<23, 1> { }; /* page mapping restriction on */
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};
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/* check for mapping restrictions */
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assert(!Ctr::P::get(Cpu::Ctr::read()));
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/* invalidate TLB */
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Cpu::Tlbiall::write(0);
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/* address space ID to zero */
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Cpu::Cidr::write(0);
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/* do not use domains, but permission bits in table */
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Cpu::Dacr::write(Cpu::Dacr::D0::bits(1));
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Cpu::Ttbcr::write(1);
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Genode::addr_t table = (Genode::addr_t)core_pd->table_base;
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Cpu::Ttbr::access_t ttbr = Cpu::Ttbr::init(table);
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Cpu::Ttbr0::write(ttbr);
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Cpu::Ttbr1::write(ttbr);
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sctlr = Cpu::Sctlr::read();
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Cpu::Sctlr::C::set(sctlr, 1);
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Cpu::Sctlr::I::set(sctlr, 1);
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Cpu::Sctlr::M::set(sctlr, 1);
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Cpu::Sctlr::write(sctlr);
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/* invalidate branch predictor */
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Cpu::Bpiall::write(0);
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return 0;
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}
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