5c7436bf10
Whether an SoC has the multiprocessing extensions can be read out from the identification registers, and does not need to be specified in each board header. Ref #3445
44 lines
924 B
C++
44 lines
924 B
C++
/*
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* \brief Generic MMU initialization for ARM
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* \author Stefan Kalkowski
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* \date 2017-04-09
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <spec/arm/cpu.h>
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void Board::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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{
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/* invalidate TLB */
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Tlbiall::write(0);
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/* address space ID to zero */
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Cidr::write(0);
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/* do not use domains, but permission bits in table */
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Dacr::write(Dacr::D0::bits(1));
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Ttbcr::write(1);
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Ttbr::access_t ttbr = Ttbr::init(table);
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Ttbr0::write(ttbr);
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Ttbr1::write(ttbr);
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Sctlr::access_t sctlr = Sctlr::read();
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Sctlr::C::set(sctlr, 1);
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Sctlr::I::set(sctlr, 1);
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Sctlr::V::set(sctlr, 1);
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Sctlr::M::set(sctlr, 1);
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Sctlr::Z::set(sctlr, 1);
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Sctlr::write(sctlr);
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/* invalidate branch predictor */
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Bpiall::write(0);
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}
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