949 lines
21 KiB
C++
949 lines
21 KiB
C++
/**
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*
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* \brief Generic AHCI controller definitions
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* \author Sebasitan Sumpf
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* \date 2015-04-29
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _AHCI__AHCI_H_
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#define _AHCI__AHCI_H_
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#include <block/request_stream.h>
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#include <os/attached_mmio.h>
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#include <os/reporter.h>
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#include <util/retry.h>
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#include <util/reconstructible.h>
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#include <platform.h>
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static bool constexpr verbose = false;
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namespace Ahci {
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struct Missing_controller : Exception { };
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class Platform;
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struct Protocol;
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struct Port;
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struct Port_base;
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struct Hba;
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using Response = Block::Request_stream::Response;
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using block_number_t = Block::block_number_t;
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using block_count_t = Block::block_count_t;
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}
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class Ahci::Platform
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{
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private :
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Data _data;
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protected:
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/**
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* Return base address and size of HBA device registers
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*/
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addr_t _mmio_base() const;
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public:
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Platform(Env &env) : _data(env) { };
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/**
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* Register interrupt signal context
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*/
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void sigh_irq(Signal_context_capability sigh);
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void ack_irq();
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/**
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* DMA
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*/
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Ram_dataspace_capability alloc_dma_buffer(size_t size);
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void free_dma_buffer(Ram_dataspace_capability ds);
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};
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/**
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* HBA definitions
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*/
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struct Ahci::Hba : Ahci::Platform,
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Mmio
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{
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Mmio::Delayer &_delayer;
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Hba(Env &env, Mmio::Delayer &delayer)
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: Platform(env), Mmio(_mmio_base()), _delayer(delayer) { }
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/**
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* Host capabilites
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*/
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struct Cap : Register<0x0, 32>
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{
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struct Np : Bitfield<0, 4> { }; /* number of ports */
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struct Ncs : Bitfield<8, 5> { }; /* number of command slots */
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struct Iss : Bitfield<20, 4> { }; /* interface speed support */
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struct Sncq : Bitfield<30, 1> { }; /* supports native command queuing */
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struct Sa64 : Bitfield<31, 1> { }; /* supports 64 bit addressing */
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};
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unsigned port_count() { return read<Cap::Np>() + 1; }
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unsigned command_slots() { return read<Cap::Ncs>() + 1; }
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bool ncq() { return !!read<Cap::Sncq>(); }
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bool supports_64bit(){ return !!read<Cap::Sa64>(); }
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/**
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* Generic host control
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*/
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struct Ghc : Register<0x4, 32>
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{
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struct Hr : Bitfield<0, 1> { }; /* hard reset */
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struct Ie : Bitfield<1, 1> { }; /* interrupt enable */
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struct Ae : Bitfield<31, 1> { }; /* AHCI enable */
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};
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/**
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* Interrupt status
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*/
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struct Is : Register<0x8, 32> { };
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void ack_irq()
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{
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write<Is>(read<Is>());
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Platform::ack_irq();
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}
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/**
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* Ports implemented
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*/
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struct Pi : Register<0xc, 32> { };
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/**
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* AHCI version
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*/
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struct Version : Register<0x10, 32>
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{
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struct Minor : Bitfield<0, 16> { };
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struct Major : Bitfield<16, 16> { };
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};
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struct Cap2 : Register<0x24, 32> { };
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void init()
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{
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/* enable AHCI */
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write<Ghc::Ae>(1);
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/* enable interrupts */
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write<Ghc::Ie>(1);
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}
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Mmio::Delayer &delayer() { return _delayer; }
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};
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/***********************************
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** AHCI commands and descriptors **
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***********************************/
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namespace Ahci {
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struct Device_fis : Mmio
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{
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struct Status : Register<0x2, 8>
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{
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/* ATAPI bits */
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struct Device_ready : Bitfield<6, 1> { };
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};
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struct Error : Register<0x3, 8> { };
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Device_fis(addr_t recv_base)
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: Mmio(recv_base + 0x40) { }
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};
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struct Command_fis : Mmio
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{
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struct Type : Register<0x0, 8> { }; /* FIS type */
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struct Bits : Register<0x1, 8, 1>
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{
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struct C : Bitfield<7, 1> { }; /* update of command register */
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};
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struct Command : Register<0x2, 8, 1> { }; /* ATA command */
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struct Features0_7 : Register<0x3, 8> { };
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/* big-endian use byte access */
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struct Lba0_7 : Register<0x4, 8> { };
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struct Lba8_15 : Register<0x5, 8> { };
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struct Lba16_23 : Register<0x6, 8> { };
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struct Lba24 : Bitset_3<Lba0_7, Lba8_15, Lba16_23> { };
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struct Device : Register<0x7, 8>
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{
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struct Lba : Bitfield<6, 1> { }; /* enable LBA mode */
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};
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/* big endian */
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struct Lba24_31 : Register<0x8, 8> { };
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struct Lba32_39 : Register<0x9, 8> { };
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struct Lba40_47 : Register<0xa, 8> { };
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struct Features8_15 : Register<0xb, 8> { };
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struct Features : Bitset_2<Features0_7, Features8_15> { };
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struct Lba48 : Bitset_3<Lba24_31, Lba32_39, Lba40_47> { };
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struct Lba : Bitset_2<Lba24, Lba48> { }; /* LBA 0 - 47 */
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/* big endian */
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struct Sector0_7 : Register<0xc, 8, 1>
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{
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struct Tag : Bitfield<3, 5> { };
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};
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struct Sector8_15 : Register<0xd, 8> { };
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struct Sector : Bitset_2<Sector0_7, Sector8_15> { }; /* sector count */
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Command_fis(addr_t base)
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: Mmio(base)
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{
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clear();
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enum { HOST_TO_DEVICE = 0x27 };
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write<Type>(HOST_TO_DEVICE);
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}
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static constexpr size_t size() { return 0x14; }
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void clear() { memset((void *)base(), 0, size()); }
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/************************
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** ATA spec commands **
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************************/
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void identify_device()
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{
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write<Bits::C>(1);
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write<Device::Lba>(0);
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write<Command>(0xec);
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}
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void dma_ext(bool read, block_number_t block_number, block_count_t block_count)
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{
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write<Bits::C>(1);
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write<Device::Lba>(1);
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/* read_dma_ext : write_dma_ext */
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write<Command>(read ? 0x25 : 0x35);
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write<Lba>(block_number);
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write<Sector>(block_count);
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}
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void fpdma(bool read, block_number_t block_number, block_count_t block_count,
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unsigned slot)
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{
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write<Bits::C>(1);
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write<Device::Lba>(1);
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/* read_fpdma : write_fpdma */
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write<Command>(read ? 0x60 : 0x61);
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write<Lba>(block_number);
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write<Features>(block_count);
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write<Sector0_7::Tag>(slot);
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}
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void atapi()
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{
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write<Bits::C>(1);
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/* packet command */
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write<Command>(0xa0);
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}
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/*
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* Sets byte count limit for PIO transfers
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*/
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void byte_count(uint16_t bytes)
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{
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write<Lba8_15>(bytes & 0xff);
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write<Lba16_23>(bytes >> 8);
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}
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};
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/**
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* AHCI command list structure header
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*/
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struct Command_header : Mmio
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{
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struct Bits : Register<0x0, 16>
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{
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struct Cfl : Bitfield<0, 5> { }; /* command FIS length */
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struct A : Bitfield<5, 1> { }; /* ATAPI command flag */
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struct W : Bitfield<6, 1> { }; /* write flag */
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struct P : Bitfield<7, 1> { }; /* prefetchable flag */
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struct C : Bitfield<10, 1> { }; /* clear busy upon R_OK */
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};
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struct Prdtl : Register<0x2, 16> { }; /* physical region descr. length */
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struct Prdbc : Register<0x4, 32> { }; /* PRD byte count */
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struct Ctba0 : Register<0x8, 32> { }; /* command table base addr (low) */
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struct Ctba0_u0 : Register<0xc, 32> { }; /* command table base addr (upper) */
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Command_header(addr_t base) : Mmio(base) { }
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void cmd_table_base(addr_t base_phys)
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{
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uint64_t addr = base_phys;
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write<Ctba0>(addr);
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write<Ctba0_u0>(addr >> 32);
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write<Prdtl>(1);
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write<Bits::Cfl>(Command_fis::size() / sizeof(unsigned));
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}
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void clear_byte_count()
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{
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write<Prdbc>(0);
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}
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void atapi_command()
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{
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write<Bits::A>(1);
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}
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static constexpr size_t size() { return 0x20; }
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};
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/**
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* ATAPI packet 12 or 16 bytes
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*/
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struct Atapi_command : Mmio
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{
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struct Command : Register<0, 8> { };
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/* LBA32 big endian */
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struct Lba24_31 : Register<0x2, 8> { };
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struct Lba16_23 : Register<0x3, 8> { };
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struct Lba8_15 : Register<0x4, 8> { };
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struct Lba0_7 : Register<0x5, 8> { };
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struct Lba24 : Bitset_3<Lba0_7, Lba8_15, Lba16_23> { };
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struct Lba : Bitset_2<Lba24, Lba24_31> { };
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/* sector count big endian */
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struct Sector8_15 : Register<0x8, 8> { };
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struct Sector0_7 : Register<0x9, 8> { };
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struct Sector : Bitset_2<Sector0_7, Sector8_15> { };
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Atapi_command(addr_t base) : Mmio(base)
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{
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memset((void *)base, 0, 16);
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}
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void read_capacity()
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{
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write<Command>(0x25);
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}
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void test_unit_ready()
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{
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write<Command>(0x0);
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}
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void read_sense()
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{
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write<Command>(0x3);
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write<Lba8_15>(18);
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}
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void read10(block_number_t block_number, block_count_t block_count)
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{
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write<Command>(0x28);
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write<Lba>(block_number);
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write<Sector>(block_count);
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}
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void start_unit()
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{
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write<Command>(0x1b);
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}
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};
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/**
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* Physical region descritpor table
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*/
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struct Prdt : Mmio
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{
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struct Dba : Register<0x0, 32> { }; /* data base address */
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struct Dbau : Register<0x4, 32> { }; /* data base address upper 32 bits */
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struct Bits : Register<0xc, 32>
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{
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struct Dbc : Bitfield<0, 22> { }; /* data byte count */
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struct Irq : Bitfield<31,1> { }; /* interrupt completion */
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};
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Prdt(addr_t base, addr_t phys, size_t bytes)
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: Mmio(base)
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{
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uint64_t addr = phys;
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write<Dba>(addr);
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write<Dbau>(addr >> 32);
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write<Bits::Dbc>(bytes > 0 ? bytes - 1 : 0);
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}
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static constexpr size_t size() { return 0x10; }
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};
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struct Command_table
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{
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Command_fis fis;
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Atapi_command atapi_cmd;
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/* in Genode we only need one PRD (for one packet) */
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Prdt prdt;
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Command_table(addr_t base,
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addr_t phys,
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size_t bytes = 0)
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: fis(base), atapi_cmd(base + 0x40),
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prdt(base + 0x80, phys, bytes)
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{ }
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static constexpr size_t size() { return 0x100; }
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};
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} /* namespace Ahci */
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/**
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* Minimalistic AHCI port structure to merely detect device signature
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*/
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struct Ahci::Port_base : Mmio
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{
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/* device signature */
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enum Signature {
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ATA_SIG = 0x101,
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ATAPI_SIG = 0xeb140101,
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ATAPI_SIG_QEMU = 0xeb140000, /* will be fixed in Qemu */
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};
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unsigned index { };
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Hba &hba;
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/**
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* Port signature
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*/
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struct Sig : Register<0x24, 32> { };
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static constexpr addr_t offset() { return 0x100; }
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static constexpr size_t size() { return 0x80; }
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Port_base(unsigned index, Hba &hba)
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: Mmio(hba.base() + offset() + (index * size())),
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index(index), hba(hba) { }
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bool implemented() const
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{
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return hba.read<Hba::Pi>() & (1u << index);
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}
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bool ata() const { return read<Sig>() == ATA_SIG; }
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bool atapi() const
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{
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unsigned sig = read<Sig>();
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return sig == ATAPI_SIG || sig == ATAPI_SIG_QEMU;
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}
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};
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struct Ahci::Protocol : Interface
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{
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virtual unsigned init(Port &port) = 0;
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virtual Block::Session::Info info() const = 0;
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virtual void handle_irq(Port &port) = 0;
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virtual Response submit(Port &port, Block::Request const request) = 0;
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virtual Block::Request completed(Port &port) = 0;
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virtual void writeable(bool rw) = 0;
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};
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/**
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* AHCI port
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*/
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struct Ahci::Port : private Port_base
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{
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using Port_base::write;
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using Port_base::read;
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using Port_base::wait_for_any;
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using Port_base::wait_for;
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using Port_base::Register_set::Polling_timeout;
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using Port_base::index;
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using Port_base::hba;
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struct Not_ready : Exception { };
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Protocol &protocol;
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Region_map &rm;
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unsigned cmd_slots = hba.command_slots();
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Ram_dataspace_capability device_ds { };
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Ram_dataspace_capability cmd_ds { };
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Ram_dataspace_capability device_info_ds { };
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addr_t cmd_list = 0;
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addr_t fis_base = 0;
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addr_t cmd_table = 0;
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addr_t device_info = 0;
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addr_t dma_base = 0; /* physical address of DMA memory */
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Port(Protocol &protocol, Region_map &rm, Hba &hba,
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unsigned index)
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:
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Port_base(index, hba),
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protocol(protocol), rm(rm)
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{
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reset();
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if (!enable())
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throw 1;
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stop();
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wait_for(hba.delayer(), Cmd::Cr::Equal(0));
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init();
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/*
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* Init protocol and determine actual number of command slots of device
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*/
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try {
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unsigned device_slots = protocol.init(*this);
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cmd_slots = min(device_slots, cmd_slots);
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} catch (Polling_timeout) {
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/* ack any pending IRQ from failed device initialization */
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ack_irq();
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throw;
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}
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}
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virtual ~Port()
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{
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if (device_ds.valid()) {
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rm.detach((void *)cmd_list);
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hba.free_dma_buffer(device_ds);
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}
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if (cmd_ds.valid()) {
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rm.detach((void *)cmd_table);
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hba.free_dma_buffer(cmd_ds);
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}
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if (device_info_ds.valid()) {
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rm.detach((void*)device_info);
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hba.free_dma_buffer(device_info_ds);
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}
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}
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/**
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* Command list base (1K length naturally aligned)
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*/
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struct Clb : Register<0x0, 32> { };
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/**
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* Command list base upper 32 bit
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*/
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struct Clbu : Register<0x4, 32> { };
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void command_list_base(addr_t phys)
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{
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uint64_t addr = phys;
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write<Clb>(addr);
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write<Clbu>(addr >> 32);
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}
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/**
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* FIS base address (256 bytes naturally aligned)
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*/
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struct Fb : Register<0x8, 32> { };
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/**
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* FIS base address upper 32 bit
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*/
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struct Fbu : Register<0xc, 32> { };
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void fis_rcv_base(addr_t phys)
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{
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|
uint64_t addr = phys;
|
|
write<Fb>(addr);
|
|
write<Fbu>(addr >> 32);
|
|
}
|
|
|
|
/**
|
|
* Port interrupt status
|
|
*/
|
|
struct Is : Register<0x10, 32, 1>
|
|
{
|
|
struct Dhrs : Bitfield<0, 1> { }; /* device to host register FIS */
|
|
struct Pss : Bitfield<1, 1> { }; /* PIO setup FIS */
|
|
struct Dss : Bitfield<2, 1> { }; /* DMA setup FIS */
|
|
struct Sdbs : Bitfield<3, 1> { }; /* Set device bit */
|
|
struct Pcs : Bitfield<6, 1> { }; /* port connect change status */
|
|
struct Prcs : Bitfield<22, 1> { }; /* PhyRdy change status */
|
|
struct Infs : Bitfield<26, 1> { }; /* interface non-fatal error */
|
|
struct Ifs : Bitfield<27, 1> { }; /* interface fatal error */
|
|
|
|
/* ncq irq */
|
|
struct Fpdma_irq : Sdbs { };
|
|
|
|
/* non-ncq irq */
|
|
struct Dma_ext_irq : Bitfield<0, 3> { };
|
|
};
|
|
|
|
void ack_irq()
|
|
{
|
|
Is::access_t status = read <Is>();
|
|
|
|
/* clear Serr.Diag.x */
|
|
if (Is::Pcs::get(status))
|
|
write<Serr::Diag::X>(0);
|
|
|
|
/* clear Serr.Diag.n */
|
|
if (Is::Prcs::get(status))
|
|
write<Serr::Diag::N>(0);
|
|
|
|
write<Is>(read<Is>());
|
|
};
|
|
|
|
/**
|
|
* Port interrupt enable
|
|
*/
|
|
struct Ie : Register<0x14, 32, 1>
|
|
{
|
|
struct Dhre : Bitfield<0, 1> { }; /* device to host register FIS interrupt */
|
|
struct Pse : Bitfield<1, 1> { }; /* PIO setup FIS interrupt */
|
|
struct Dse : Bitfield<2, 1> { }; /* DMA setup FIS interrupt */
|
|
struct Sdbe : Bitfield<3, 1> { }; /* set device bits FIS interrupt (ncq) */
|
|
struct Ufe : Bitfield<4, 1> { }; /* unknown FIS */
|
|
struct Dpe : Bitfield<5, 1> { }; /* descriptor processed */
|
|
struct Ifne : Bitfield<26, 1> { }; /* interface non-fatal error */
|
|
struct Ife : Bitfield<27, 1> { }; /* interface fatal error */
|
|
struct Hbde : Bitfield<28, 1> { }; /* host bus data error */
|
|
struct Hbfe : Bitfield<29, 1> { }; /* host bus fatal error */
|
|
struct Tfee : Bitfield<30, 1> { }; /* task file error */
|
|
};
|
|
|
|
void interrupt_enable()
|
|
{
|
|
Ie::access_t ie = 0;
|
|
Ie::Dhre::set(ie, 1);
|
|
Ie::Pse::set(ie, 1);
|
|
Ie::Dse::set(ie, 1);
|
|
Ie::Sdbe::set(ie, 1);
|
|
Ie::Ufe::set(ie, 1);
|
|
Ie::Dpe::set(ie, 1);
|
|
Ie::Ifne::set(ie, 1);
|
|
Ie::Hbde::set(ie, 1);
|
|
Ie::Hbfe::set(ie, 1);
|
|
Ie::Tfee::set(ie, 1);
|
|
write<Ie>(~0U);
|
|
}
|
|
|
|
/**
|
|
* Port command
|
|
*/
|
|
struct Cmd : Register<0x18, 32>
|
|
{
|
|
struct St : Bitfield<0, 1> { }; /* start */
|
|
struct Sud : Bitfield<1, 1> { }; /* spin-up device */
|
|
struct Pod : Bitfield<2, 1> { }; /* power-up device */
|
|
struct Fre : Bitfield<4, 1> { }; /* FIS receive enable */
|
|
struct Fr : Bitfield<14, 1> { }; /* FIS receive running */
|
|
struct Cr : Bitfield<15, 1> { }; /* command list running */
|
|
struct Atapi : Bitfield<24, 1> { };
|
|
struct Icc : Bitfield<28, 4> { }; /* interface communication control */
|
|
};
|
|
|
|
void start()
|
|
{
|
|
if (read<Cmd::St>())
|
|
return;
|
|
|
|
try {
|
|
wait_for(hba.delayer(), Tfd::Sts_bsy::Equal(0));
|
|
} catch (Polling_timeout) {
|
|
error("HBA busy unable to start command processing.");
|
|
return;
|
|
}
|
|
|
|
try {
|
|
wait_for(hba.delayer(), Tfd::Sts_drq::Equal(0));
|
|
} catch (Polling_timeout) {
|
|
error("HBA in DRQ unable to start command processing.");
|
|
return;
|
|
}
|
|
|
|
write<Cmd::St>(1);
|
|
}
|
|
|
|
void stop()
|
|
{
|
|
if (!(read<Ci>() | read<Sact>()))
|
|
write<Cmd::St>(0);
|
|
}
|
|
|
|
void power_up()
|
|
{
|
|
Cmd::access_t cmd = read<Cmd>();
|
|
Cmd::Sud::set(cmd, 1);
|
|
Cmd::Pod::set(cmd, 1);
|
|
Cmd::Fre::set(cmd, 1);
|
|
write<Cmd>(cmd);
|
|
}
|
|
|
|
/**
|
|
* Task file data
|
|
*/
|
|
struct Tfd : Register<0x20, 32>
|
|
{
|
|
struct Sts_drq : Bitfield<3, 1> { }; /* indicates data transfer request */
|
|
struct Sts_bsy : Bitfield<7, 1> { }; /* interface is busy */
|
|
};
|
|
|
|
/**
|
|
* Serial ATA status
|
|
*/
|
|
struct Ssts : Register<0x28, 32>
|
|
{
|
|
struct Dec : Bitfield<0, 4> /* device detection */
|
|
{
|
|
enum {
|
|
NONE = 0x0,
|
|
ESTABLISHED = 0x3
|
|
};
|
|
};
|
|
struct Ipm : Bitfield<8, 4> /* interface power mgmt */
|
|
{
|
|
enum {
|
|
ACTIVE = 0x1,
|
|
SUSPEND = 0x2,
|
|
};
|
|
};
|
|
};
|
|
|
|
bool enable()
|
|
{
|
|
Ssts::access_t status = read<Ssts>();
|
|
if (Ssts::Dec::get(status) == Ssts::Dec::NONE)
|
|
return false;
|
|
|
|
/* if in power-mgmt state (partial or slumber) */
|
|
if (Ssts::Ipm::get(status) & Ssts::Ipm::SUSPEND) {
|
|
/* try to wake up device */
|
|
write<Cmd::Icc>(Ssts::Ipm::ACTIVE);
|
|
|
|
retry<Not_ready>(
|
|
[&] {
|
|
if ((Ssts::Dec::get(status) != Ssts::Dec::ESTABLISHED) ||
|
|
!(Ssts::Ipm::get(status) & Ssts::Ipm::ACTIVE))
|
|
throw Not_ready();
|
|
},
|
|
[&] {
|
|
hba.delayer().usleep(1000);
|
|
status = read<Ssts>();
|
|
}, 10);
|
|
}
|
|
|
|
return ((Ssts::Dec::get(status) == Ssts::Dec::ESTABLISHED) &&
|
|
(Ssts::Ipm::get(status) & Ssts::Ipm::ACTIVE));
|
|
}
|
|
|
|
/**
|
|
* Serial ATA control
|
|
*/
|
|
struct Sctl : Register<0x2c, 32>
|
|
{
|
|
struct Det : Bitfield<0, 4> { }; /* device dectection initialization */
|
|
struct Ipmt : Bitfield<8, 4> { }; /* allowed power management transitions */
|
|
};
|
|
|
|
void reset()
|
|
{
|
|
if (read<Cmd::St>())
|
|
warning("CMD.ST bit set during device reset --> unknown behavior");
|
|
|
|
write<Sctl::Det>(1);
|
|
hba.delayer().usleep(1000);
|
|
write<Sctl::Det>(0);
|
|
|
|
try {
|
|
wait_for(hba.delayer(), Ssts::Dec::Equal(Ssts::Dec::ESTABLISHED));
|
|
} catch (Polling_timeout) {
|
|
warning("Port reset failed");
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Serial ATA error
|
|
*/
|
|
struct Serr : Register<0x30, 32>
|
|
{
|
|
struct Diag : Register<0x2, 16>
|
|
{
|
|
struct N : Bitfield<0, 1> { }; /* PhyRdy change */
|
|
struct X : Bitfield<10, 1> { }; /* exchanged */
|
|
};
|
|
};
|
|
|
|
void clear_serr() { write<Serr>(read<Serr>()); }
|
|
|
|
/**
|
|
* Serial ATA active (strict write)
|
|
*/
|
|
struct Sact : Register<0x34, 32, true> { };
|
|
|
|
/**
|
|
* Command issue (strict write)
|
|
*/
|
|
struct Ci : Register<0x38, 32, true> { };
|
|
|
|
void init()
|
|
{
|
|
/* stop command list processing */
|
|
stop();
|
|
|
|
/* setup command list/table */
|
|
setup_memory();
|
|
|
|
/* disallow all power-management transitions */
|
|
write<Sctl::Ipmt>(0x3);
|
|
|
|
/* power-up device */
|
|
power_up();
|
|
|
|
/* reset port */
|
|
reset();
|
|
|
|
/* clean error register */
|
|
clear_serr();
|
|
|
|
/* enable required interrupts */
|
|
interrupt_enable();
|
|
|
|
/* acknowledge all pending interrupts */
|
|
ack_irq();
|
|
hba.ack_irq();
|
|
}
|
|
|
|
void setup_memory()
|
|
{
|
|
device_ds = hba.alloc_dma_buffer(0x1000);
|
|
|
|
/* command list 1K */
|
|
addr_t phys = Dataspace_client(device_ds).phys_addr();
|
|
cmd_list = (addr_t)rm.attach(device_ds);
|
|
command_list_base(phys);
|
|
|
|
/* receive FIS base 256 byte */
|
|
fis_base = cmd_list + 1024;
|
|
|
|
/*
|
|
* Set fis receive base, clear Fre (FIS receive) before and wait for FR
|
|
* (FIS receive running) to clear
|
|
*/
|
|
write<Cmd::Fre>(0);
|
|
wait_for(hba.delayer(), Cmd::Fr::Equal(0));
|
|
fis_rcv_base(phys + 1024);
|
|
|
|
/* command table */
|
|
size_t cmd_size = align_addr(cmd_slots * Command_table::size(), 12);
|
|
cmd_ds = hba.alloc_dma_buffer(cmd_size);
|
|
cmd_table = (addr_t)rm.attach(cmd_ds);
|
|
phys = (addr_t)Dataspace_client(cmd_ds).phys_addr();
|
|
|
|
/* set command table addresses in command list */
|
|
for (unsigned i = 0; i < cmd_slots; i++) {
|
|
Command_header h(cmd_list + (i * Command_header::size()));
|
|
h.cmd_table_base(phys + (i * Command_table::size()));
|
|
}
|
|
|
|
/* dataspace for device info */
|
|
device_info_ds = hba.alloc_dma_buffer(0x1000);
|
|
device_info = rm.attach(device_info_ds);
|
|
}
|
|
|
|
addr_t command_table_addr(unsigned slot)
|
|
{
|
|
return cmd_table + (slot * Command_table::size());
|
|
};
|
|
|
|
addr_t command_header_addr(unsigned slot)
|
|
{
|
|
return cmd_list + (slot * Command_header::size());
|
|
}
|
|
|
|
void execute(unsigned slot)
|
|
{
|
|
start();
|
|
write<Ci>(1U << slot);
|
|
}
|
|
|
|
bool sanity_check(Block::Request const &request)
|
|
{
|
|
Block::Session::Info const i = info();
|
|
|
|
/* max. PRDT size is 4MB */
|
|
if (request.operation.count * i.block_size > 4 * 1024 * 1024) {
|
|
error("error: maximum supported packet size is 4MB");
|
|
return false;
|
|
}
|
|
|
|
/* sanity check */
|
|
if (request.operation.count + request.operation.block_number > i.block_count) {
|
|
error("error: requested blocks are outside of device");
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
Ram_dataspace_capability alloc_buffer(size_t size)
|
|
{
|
|
if (dma_base) return Ram_dataspace_capability();
|
|
|
|
Ram_dataspace_capability dma = hba.alloc_dma_buffer(size);
|
|
dma_base = Dataspace_client(dma).phys_addr();
|
|
return dma;
|
|
}
|
|
|
|
void free_buffer(Ram_dataspace_capability ds)
|
|
{
|
|
dma_base = 0;
|
|
hba.free_dma_buffer(ds);
|
|
}
|
|
|
|
/**********************
|
|
** Protocol wrapper **
|
|
**********************/
|
|
|
|
|
|
Block::Session::Info info() const { return protocol.info(); }
|
|
void handle_irq() { protocol.handle_irq(*this); }
|
|
|
|
Response submit(Block::Request const request) {
|
|
return protocol.submit(*this, request); }
|
|
|
|
template <typename FN>
|
|
void for_one_completed_request(FN const &fn)
|
|
{
|
|
Block::Request request = protocol.completed(*this);
|
|
if (!request.operation.valid()) return;
|
|
|
|
request.success = true;
|
|
fn(request);
|
|
}
|
|
|
|
void writeable(bool rw) { protocol.writeable(rw); }
|
|
};
|
|
|
|
#endif /* _AHCI__AHCI_H_ */
|