702 lines
16 KiB
C++
702 lines
16 KiB
C++
/*
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* \brief DesignWare Multimedia Card interface
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* \author Sebastian Sumpf
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* \date 2013-03-06
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _DWMMC_H_
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#define _DWMMC_H_
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#include <drivers/board_base.h>
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#include <irq_session/connection.h>
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#include <os/attached_ram_dataspace.h>
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#include <util/mmio.h>
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#include <sd_card.h>
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struct Dwmmc : Genode::Mmio
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{
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enum { verbose = false };
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/*
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* These apply to card controller 0 and 1 only
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*/
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enum {
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HOST_FREQ = 52000000, /* Hz */
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CLK_FREQ = 400000000, /* Hz */
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/* CLK_FREQ / (2 * CLK_DIV <= HOST_FREQ) */
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CLK_DIV_52Mhz = 4,
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CLK_DIV_400Khz = 0xff,
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};
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Dwmmc(Genode::addr_t base) : Genode::Mmio(base) { }
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template <Genode::off_t OFFSET, bool STRICT_WRITE = false>
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struct Register : Genode::Mmio::Register<OFFSET, 32, STRICT_WRITE> { };
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/**
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* Control register
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*/
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struct Ctrl : Register<0x0>
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{
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/* Controller/FIFO/DMA reset */
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struct Reset : Bitfield<0, 3> { };
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struct Global_interrupt : Bitfield<4, 1> { };
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struct Dma_enable : Bitfield<5, 1> { };
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struct Use_internal_dmac : Bitfield<25, 1> { };
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};
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/**
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* Power-enable register
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*/
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struct Pwren : Register<0x4> { };
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/**
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* Clock-devider register
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*/
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struct Clkdiv : Register<0x8> { };
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/**
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* Clock-enable register
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*/
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struct Clkena : Register<0x10> { };
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/**
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* Timeout register
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*/
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struct Tmout : Register<0x14> { };
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/**
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* Card-type register
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*/
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struct Ctype : Register<0x18, true> { };
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/**
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* Block-size register
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*/
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struct Blksize : Register<0x1c> { };
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/**
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* Byte-count register
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*/
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struct Bytcnt : Register<0x20> { };
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/**
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* Interrupt-mask register
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*/
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struct Intmask : Register<0x24> { };
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/**
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* Command-argument register
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*/
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struct Cmdarg : Register<0x28> { };
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/**
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* Command register
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*/
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struct Cmd : Register<0x2c>
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{
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struct Index : Bitfield<0, 6> { };
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struct Rsp_type : Bitfield<6, 3>
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{
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enum Response { RESPONSE_NONE = 0,
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RESPONSE_48_BIT = 1,
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RESPONSE_48_BIT_WITH_BUSY = 5,
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RESPONSE_136_BIT = 7,
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};
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};
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struct Data_expected : Bitfield<9, 1> { };
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struct Write : Bitfield<10, 1> { };
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struct Wait_prvdata_complete : Bitfield<13, 1> { };
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struct Init_sequence : Bitfield<15, 1> { };
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struct Update_clock_registers_only : Bitfield<21, 1> { };
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struct Use_hold_reg : Bitfield<29, 1> { };
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struct Start_cmd : Bitfield<31, 1> { };
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};
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/**
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* Response bits 0..127
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*/
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struct Rsp0 : Register<0x30> { };
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struct Rsp1 : Register<0x34> { };
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struct Rsp2 : Register<0x38> { };
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struct Rsp3 : Register<0x3c> { };
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/**
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* Interrupt-status register
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*/
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struct Mintsts : Register<0x40> { };
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struct Rintsts : Register<0x44, true>
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{
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struct Response_error : Bitfield<1, 1> { };
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struct Data_transfer_over : Bitfield<3, 1> { };
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struct Command_done : Bitfield<2, 1> { };
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struct Data_crc_error : Bitfield<7, 1> { };
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struct Response_timeout : Bitfield<8, 1> { };
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struct Data_read_timeout : Bitfield<9, 1> { };
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};
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/**
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* Status register
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*/
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struct Status : Register<0x48>
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{
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struct Data_busy : Bitfield<9, 1> { };
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};
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/**
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* Fifo-threshold register
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*/
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struct Fifoth : Register<0x4c> { };
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/**
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* Bus-mode register
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*/
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struct Bmod : Register<0x80, true>
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{
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struct Fixed_burst : Bitfield<1, 1> { };
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struct Idmac_enable : Bitfield<7, 1> { };
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};
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/**
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* Poll demant register
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*/
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struct Pldmnd : Register<0x84> { };
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struct Idsts : Register<0x8c> { };
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struct Idinten : Register<0x90, true> { };
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/**
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* Descriptor list base-address register
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*/
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struct Dbaddr : Register<0x88> { };
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/**
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* Clock selector
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*/
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struct Clksel : Register<0x9c> { };
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struct Emmc_ddr_req : Register<0x10c, true> { };
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typedef Genode::size_t size_t;
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void powerup()
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{
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write<Pwren>(1);
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}
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bool reset(Delayer &delayer)
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{
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/* set all three bits */
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write<Ctrl::Reset>(0x7);
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if (!wait_for<Ctrl::Reset>(0, delayer, 100, 1000)) {
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PERR("Could not reset host contoller");
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return false;
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}
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return true;
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}
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void reset_fifo(Delayer &delayer)
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{
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write<Ctrl::Reset>(0x2);
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if (!wait_for<Ctrl::Reset>(0, delayer, 100, 1000))
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PERR("Could not reset fifo");
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}
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void disable_irq()
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{
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write<Rintsts>(~0U);
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write<Intmask>(0);
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}
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enum Bus_width {
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BUS_WIDTH_1 = 0,
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BUS_WIDTH_4 = 1,
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BUS_WIDTH_8 = 1 << 16,
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};
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void bus_width(Bus_width bus_width)
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{
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write<Ctype>(bus_width);
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}
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bool update_clock_registers(Delayer &delayer)
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{
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Cmd::access_t cmd = 0;
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Cmd::Wait_prvdata_complete::set(cmd, 1);
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Cmd::Update_clock_registers_only::set(cmd, 1);
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Cmd::Start_cmd::set(cmd, 1);
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write<Cmd>(cmd);
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if (!wait_for<Cmd::Start_cmd>(0, delayer)) {
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PERR("Update clock registers failed");
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return false;
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}
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return true;
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}
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bool setup_bus(unsigned clock_div, Delayer &delayer)
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{
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/* set host clock divider */
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write<Clkdiv>(clock_div);
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if (!update_clock_registers(delayer))
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return false;
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/* enable clock for card 1 */
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write<Clkena>(0x1);
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if (!update_clock_registers(delayer))
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return false;
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delayer.usleep(10 * 1000);
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return true;
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}
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};
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struct Exynos5_msh_controller : private Dwmmc, Sd_card::Host_controller
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{
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private:
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enum { BLOCK_SIZE = 512 };
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/**
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* DMA descriptpor
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*/
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struct Idmac_desc
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{
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enum Flags {
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NONE = 0,
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DIC = 1 << 1,
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LD = 1 << 2,
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FS = 1 << 3,
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CH = 1 << 4,
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ER = 1 << 5,
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OWN = 1 << 31,
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};
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unsigned flags;
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unsigned bytes;
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unsigned addr;
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unsigned next;
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size_t set(size_t block_count, Genode::addr_t phys_addr, Flags flag)
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{
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enum { MAX_BLOCKS = 8 };
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flags = OWN | flag | (block_count <= MAX_BLOCKS ? LD : (CH | DIC));
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bytes = ((block_count < MAX_BLOCKS) ? block_count : MAX_BLOCKS) * BLOCK_SIZE;
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addr = phys_addr;
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return block_count < MAX_BLOCKS ? 0 : block_count - MAX_BLOCKS;
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}
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void dump() { PDBG("this: %p f: %x bytes: %u, addr: %x next: %x", this, flags, bytes, addr, next); }
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};
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/*
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* DMA descriptors
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*/
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enum { IDMAC_DESC_MAX_ENTRIES = 1024 /* can be up to 65536 */};
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Genode::Attached_ram_dataspace _idmac_desc_ds;
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Idmac_desc * const _idmac_desc;
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Genode::addr_t const _idmac_desc_phys;
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Delayer &_delayer;
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Sd_card::Card_info _card_info;
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Genode::Irq_connection _irq;
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Genode::Signal_receiver _irq_rec;
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Genode::Signal_context _irq_ctx;
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Sd_card::Card_info _init()
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{
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using namespace Sd_card;
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powerup();
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if (!reset(_delayer))
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throw Detection_failed();
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write<Emmc_ddr_req>(0x1);
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disable_irq();
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write<Tmout>(~0U);
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write<Idinten>(0);
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write<Bmod>(1);
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write<Bytcnt>(0);
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write<Fifoth>(0x203f0040);
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/* set to one bit transfer Bit */
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if (!setup_bus(CLK_DIV_400Khz, _delayer))
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throw Detection_failed();
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bus_width(BUS_WIDTH_1);
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if (!issue_command(Go_idle_state())) {
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PWRN("Go_idle_state command failed");
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throw Detection_failed();
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}
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_delayer.usleep(2000);
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if (!issue_command(Send_if_cond())) {
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PWRN("Send_if_cond command failed");
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throw Detection_failed();
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}
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/* if this succeeds it is an SD card */
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if ((read<Rsp0>() & 0xff) == 0xaa)
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PINF("Found SD card");
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/*
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* We need to issue the same Mmc_send_op_cond command multiple
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* times. The first time, we receive the status information. On
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* subsequent attempts, the response tells us that the card is
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* busy. Usually, the command is issued twice. We give up if the
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* card is not reaching busy state after one second.
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*/
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unsigned i = 1000;
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unsigned voltages = 0x300080;
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unsigned arg = 0;
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for (; i > 0; --i) {
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if (!issue_command(Mmc_send_op_cond(arg, true))) {
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PWRN("Sd_send_op_cond command failed");
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throw Detection_failed();
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}
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arg = read<Rsp0>();
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arg = (voltages & (arg & 0x007FFF80)) | (arg & 0x60000000);
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_delayer.usleep(1000);
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if (Ocr::Busy::get(read<Rsp0>()))
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break;
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}
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if (i == 0) {
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PERR("Send_op_cond timed out, could no power-on SD/MMC card");
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throw Detection_failed();
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}
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Card_info card_info = _detect_mmc();
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/* switch frequency to high speed */
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enum { EXT_CSD_HS_TIMING = 185 };
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if (!issue_command(Mmc_switch(EXT_CSD_HS_TIMING, 1))) {
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PERR("Error setting high speed frequency");
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throw Detection_failed();
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}
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enum { EXT_CSD_BUS_WIDTH = 183 };
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/* set card to 8 bit */
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if (!issue_command(Mmc_switch(EXT_CSD_BUS_WIDTH, 2))) {
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PERR("Error setting card bus width");
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throw Detection_failed();
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}
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bus_width(BUS_WIDTH_8);
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/* set to eight bit transfer Bit */
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if (!setup_bus(CLK_DIV_52Mhz, _delayer)) {
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PERR("Error setting bus to high speed");
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throw Detection_failed();
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}
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/*
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* Enable Interrupts data read timeout | data transfer done | response
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* error
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*/
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write<Intmask>(0x28a);
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write<Ctrl::Global_interrupt>(1);
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return card_info;
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}
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bool _setup_idmac_descriptor_table(size_t block_count,
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Genode::addr_t phys_addr)
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{
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size_t const max_idmac_block_count = IDMAC_DESC_MAX_ENTRIES * 8;
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if (block_count > max_idmac_block_count) {
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PERR("Block request too large");
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return false;
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}
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reset_fifo(_delayer);
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Idmac_desc::Flags flags = Idmac_desc::FS;
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size_t b = block_count;
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int index = 0;
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for (index = 0; b;
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index++, phys_addr += 0x1000, flags = Idmac_desc::NONE) {
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b = _idmac_desc[index].set(b, phys_addr, flags);
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_idmac_desc[index].next = _idmac_desc_phys + ((index + 1) * sizeof(Idmac_desc));
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}
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_idmac_desc[index].next = (unsigned)_idmac_desc;
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_idmac_desc[index].flags |= Idmac_desc::ER;
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write<Dbaddr>(_idmac_desc_phys);
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write<Ctrl::Dma_enable>(1);
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write<Ctrl::Use_internal_dmac>(1);
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write<Bmod::Fixed_burst>(1);
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write<Bmod::Idmac_enable>(1);
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write<Blksize>(BLOCK_SIZE);
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write<Bytcnt>(BLOCK_SIZE * block_count);
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write<Pldmnd>(1);
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return true;
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}
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void _wait_for_irq()
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{
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/*
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* Acknowledge the IRQ first to implicitly activate
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* receiving of further IRQ signals on the first usage
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* of this method.
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*/
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_irq.ack_irq();
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_irq_rec.wait_for_signal();
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}
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bool _wait_for_transfer_complete()
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{
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while (1) {
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_wait_for_irq();
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if (read<Rintsts::Data_transfer_over>()) {
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write<Rintsts>(~0U);
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return true;
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}
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if (read<Rintsts::Response_error>()) {
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PERR("Response error");
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return false;
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}
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if (read<Rintsts::Data_read_timeout>()) {
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PERR("Data read timeout");
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return false;
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}
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if (read<Rintsts::Data_crc_error>()) {
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PERR("CRC error");
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return false;
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}
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}
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}
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public:
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enum { IRQ_NUMBER = Genode::Board_base::SDMMC0_IRQ };
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Exynos5_msh_controller(Server::Entrypoint &ep,
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Genode::addr_t const mmio_base, Delayer &delayer,
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bool use_dma)
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: Dwmmc(mmio_base),
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_idmac_desc_ds(Genode::env()->ram_session(),
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IDMAC_DESC_MAX_ENTRIES*sizeof(Idmac_desc),
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Genode::UNCACHED),
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_idmac_desc(_idmac_desc_ds.local_addr<Idmac_desc>()),
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_idmac_desc_phys(Genode::Dataspace_client(_idmac_desc_ds.cap()).phys_addr()),
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_delayer(delayer), _card_info(_init()), _irq(IRQ_NUMBER)
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{
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_irq.sigh(_irq_rec.manage(&_irq_ctx));
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}
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~Exynos5_msh_controller() { _irq_rec.dissolve(&_irq_ctx); }
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bool _issue_command(Sd_card::Command_base const &command)
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{
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if (verbose)
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PLOG("-> index=0x%08x, arg=0x%08x, rsp_type=%d",
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command.index, command.arg, command.rsp_type);
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if (!wait_for<Status::Data_busy>(0, _delayer, 10000, 100)) {
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PERR("wait for State::Data_busy timed out %x", read<Status>());
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return false;
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}
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write<Rintsts>(~0UL);
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/* write command argument */
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write<Cmdarg>(command.arg);
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Cmd::access_t cmd = 0;
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Cmd::Index::set(cmd, command.index);
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if (command.transfer != Sd_card::TRANSFER_NONE) {
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/* set data-direction bit depending on the command */
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bool const write = command.transfer == Sd_card::TRANSFER_WRITE;
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Cmd::Data_expected::set(cmd, 1);
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Cmd::Write::set(cmd, write ? 1 : 0);
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}
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Cmd::access_t rsp_type = 0;
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switch (command.rsp_type) {
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case Sd_card::RESPONSE_NONE: rsp_type = Cmd::Rsp_type::RESPONSE_NONE; break;
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case Sd_card::RESPONSE_136_BIT: rsp_type = Cmd::Rsp_type::RESPONSE_136_BIT; break;
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case Sd_card::RESPONSE_48_BIT: rsp_type = Cmd::Rsp_type::RESPONSE_48_BIT; break;
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case Sd_card::RESPONSE_48_BIT_WITH_BUSY: rsp_type = Cmd::Rsp_type::RESPONSE_48_BIT_WITH_BUSY; break;
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}
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Cmd::Rsp_type::set(cmd, rsp_type);
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Cmd::Start_cmd::set(cmd, 1);
|
|
Cmd::Use_hold_reg::set(cmd ,1);
|
|
Cmd::Wait_prvdata_complete::set(cmd, 1);
|
|
|
|
if (command.index == 0)
|
|
Cmd::Init_sequence::set(cmd, 1);
|
|
|
|
/* issue command */
|
|
write<Cmd>(cmd);
|
|
|
|
if (!wait_for<Rintsts::Command_done>(1, _delayer, 10000, 100)) {
|
|
PERR("Command failed Rintst: %x Mintst: %x Status: %x", read<Rintsts>(), read<Mintsts>(), read<Status>());
|
|
|
|
if (read<Rintsts::Response_timeout>())
|
|
PWRN("timeout");
|
|
|
|
if (read<Rintsts::Response_error>())
|
|
PWRN("Repsonse error");
|
|
|
|
return false;
|
|
}
|
|
|
|
if (verbose)
|
|
PDBG("IRQ: Rintsts %x transfer %s", read<Rintsts>(),
|
|
command.transfer == Sd_card::TRANSFER_NONE ? "none" : "data");
|
|
|
|
/* acknowledge interrupt */
|
|
write<Rintsts::Command_done>(1);
|
|
|
|
_delayer.usleep(100);
|
|
|
|
return true;
|
|
}
|
|
|
|
Sd_card::Cid _read_cid()
|
|
{
|
|
Sd_card::Cid cid;
|
|
cid.raw_0 = read<Rsp0>();
|
|
cid.raw_1 = read<Rsp1>();
|
|
cid.raw_2 = read<Rsp2>();
|
|
cid.raw_3 = read<Rsp3>();
|
|
return cid;
|
|
}
|
|
|
|
Sd_card::Csd _read_csd()
|
|
{
|
|
Sd_card::Csd csd;
|
|
csd.csd0 = read<Rsp0>();
|
|
csd.csd1 = read<Rsp1>();
|
|
csd.csd2 = read<Rsp2>();
|
|
csd.csd3 = read<Rsp3>();
|
|
return csd;
|
|
}
|
|
|
|
unsigned _read_rca() { return 0; }
|
|
|
|
size_t _read_ext_csd()
|
|
{
|
|
using namespace Genode;
|
|
Attached_ram_dataspace ds(env()->ram_session(), 0x1000, UNCACHED);
|
|
|
|
addr_t phys = Genode::Dataspace_client(ds.cap()).phys_addr();
|
|
_setup_idmac_descriptor_table(1, phys);
|
|
|
|
if (!issue_command(Sd_card::Mmc_send_ext_csd()))
|
|
throw Detection_failed();
|
|
|
|
if (!wait_for<Rintsts::Data_transfer_over>(1, _delayer)) {
|
|
PERR("Error retrieving extented CSD");
|
|
throw Detection_failed();
|
|
}
|
|
/* clear IRQ */
|
|
write<Rintsts::Data_transfer_over>(1);
|
|
|
|
/* contruct extented CSD */
|
|
Sd_card::Ext_csd csd((addr_t)ds.local_addr<addr_t>());
|
|
|
|
/* read revision */
|
|
if (csd.read<Sd_card::Ext_csd::Revision>() < 2) {
|
|
PERR("Extented CSD revision is < 2");
|
|
throw Detection_failed();
|
|
}
|
|
|
|
/* return sector count */
|
|
uint64_t capacity = csd.read<Sd_card::Ext_csd::Sector_count>() * BLOCK_SIZE;
|
|
|
|
/* to MB */
|
|
return capacity / (1024 * 1024);
|
|
}
|
|
|
|
Sd_card::Card_info card_info() const
|
|
{
|
|
return _card_info;
|
|
}
|
|
|
|
bool read_blocks_dma(Block::sector_t block_number, size_t block_count,
|
|
Genode::addr_t buffer_phys)
|
|
{
|
|
if (!_setup_idmac_descriptor_table(block_count, buffer_phys))
|
|
return false;
|
|
|
|
if (!_issue_command(Sd_card::Read_multiple_block(block_number))) {
|
|
PERR("Read_multiple_block failed, Status: 0x%08x", read<Status>());
|
|
return false;
|
|
}
|
|
|
|
bool complete = _wait_for_transfer_complete();
|
|
|
|
if (!_issue_command(Sd_card::Stop_transmission())) {
|
|
PERR("Unable to stop transmission");
|
|
return false;
|
|
}
|
|
|
|
return complete;
|
|
}
|
|
|
|
bool write_blocks_dma(Block::sector_t block_number, size_t block_count,
|
|
Genode::addr_t buffer_phys)
|
|
{
|
|
if (!_setup_idmac_descriptor_table(block_count, buffer_phys))
|
|
return false;
|
|
|
|
if (!_issue_command(Sd_card::Write_multiple_block(block_number))) {
|
|
PERR("Read_multiple_block failed, Status: 0x%08x", read<Status>());
|
|
return false;
|
|
}
|
|
|
|
bool complete = _wait_for_transfer_complete();
|
|
|
|
if (!_issue_command(Sd_card::Stop_transmission())) {
|
|
PERR("Unable to stop transmission");
|
|
return false;
|
|
}
|
|
|
|
return complete;
|
|
}
|
|
};
|
|
|
|
#endif /* _DWMMC_H_ */
|