314 lines
8.1 KiB
C++
314 lines
8.1 KiB
C++
/*
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* \brief Gpio driver for the OMAP4
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* \author Ivan Loskutov <ivan.loskutov@ksyslabs.org>
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2012-06-23
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*/
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/*
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* Copyright (C) 2012 Ksys Labs LLC
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _DRIVER_H_
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#define _DRIVER_H_
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/* Genode includes */
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#include <drivers/board_base.h>
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#include <gpio/driver.h>
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#include <irq_session/connection.h>
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#include <timer_session/connection.h>
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/* local includes */
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#include "gpio.h"
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static int verbose = 0;
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class Omap4_driver : public Gpio::Driver
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{
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private:
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enum {
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PIN_SHIFT = 5,
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MAX_BANKS = 6,
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MAX_PINS = 32
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};
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struct Timer_delayer : Timer::Connection, Genode::Mmio::Delayer
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{
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/**
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* Implementation of 'Delayer' interface
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*/
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void usleep(unsigned us) { Timer::Connection::usleep(us); }
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} _delayer;
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class Gpio_bank
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{
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private:
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Gpio_reg _reg;
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Genode::Irq_connection _irq;
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Genode::Signal_rpc_member<Gpio_bank> _dispatcher;
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Genode::Signal_context_capability _sig_cap[MAX_PINS];
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bool _irq_enabled[MAX_PINS];
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void _handle(unsigned)
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{
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_reg.write<Gpio_reg::Irqstatus_0>(0xffffffff);
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unsigned long status = _reg.read<Gpio_reg::Irqstatus_0>();
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for(unsigned i = 0; i < MAX_PINS; i++) {
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if ((status & (1 << i)) && _irq_enabled[i] &&
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_sig_cap[i].valid())
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Genode::Signal_transmitter(_sig_cap[i]).submit();
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}
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_irq.ack_irq();
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}
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public:
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Gpio_bank(Server::Entrypoint &ep,
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Genode::addr_t base, Genode::size_t size,
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unsigned irq)
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: _reg(base, size), _irq(irq),
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_dispatcher(ep, *this, &Gpio_bank::_handle)
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{
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for (unsigned i = 0; i < MAX_PINS; i++)
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_irq_enabled[i] = false;
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_irq.sigh(_dispatcher);
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_irq.ack_irq();
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}
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Gpio_reg* regs() { return &_reg; }
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void irq(int pin, bool enable)
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{
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if (enable) {
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_reg.write<Gpio_reg::Irqstatus_0>(1 << pin);
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_reg.write<Gpio_reg::Irqstatus_set_0>(1 << pin);
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}
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else
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_reg.write<Gpio_reg::Irqstatus_clr_0>(1 << pin);
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_irq_enabled[pin] = enable;
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}
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void ack_irq(int pin) { PDBG("not implemented"); }
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void sigh(int pin, Genode::Signal_context_capability cap) {
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_sig_cap[pin] = cap; }
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};
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Server::Entrypoint &_ep;
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Gpio_bank _gpio_bank_0;
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Gpio_bank _gpio_bank_1;
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Gpio_bank _gpio_bank_2;
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Gpio_bank _gpio_bank_3;
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Gpio_bank _gpio_bank_4;
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Gpio_bank _gpio_bank_5;
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Gpio_bank *_gpio_bank(int gpio)
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{
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switch (gpio >> PIN_SHIFT) {
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case 0:
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return &_gpio_bank_0;
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case 1:
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return &_gpio_bank_1;
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case 2:
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return &_gpio_bank_2;
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case 3:
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return &_gpio_bank_3;
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case 4:
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return &_gpio_bank_4;
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case 5:
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return &_gpio_bank_5;
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}
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PERR("no Gpio_bank for pin %d available", gpio);
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return 0;
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}
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int _gpio_index(int gpio) { return gpio & 0x1f; }
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Omap4_driver(Server::Entrypoint &ep)
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:
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_ep(ep),
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_gpio_bank_0(_ep, Genode::Board_base::GPIO1_MMIO_BASE, Genode::Board_base::GPIO1_MMIO_SIZE,
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Genode::Board_base::GPIO1_IRQ),
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_gpio_bank_1(_ep, Genode::Board_base::GPIO2_MMIO_BASE, Genode::Board_base::GPIO2_MMIO_SIZE,
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Genode::Board_base::GPIO2_IRQ),
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_gpio_bank_2(_ep, Genode::Board_base::GPIO3_MMIO_BASE, Genode::Board_base::GPIO3_MMIO_SIZE,
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Genode::Board_base::GPIO3_IRQ),
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_gpio_bank_3(_ep, Genode::Board_base::GPIO4_MMIO_BASE, Genode::Board_base::GPIO4_MMIO_SIZE,
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Genode::Board_base::GPIO4_IRQ),
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_gpio_bank_4(_ep, Genode::Board_base::GPIO5_MMIO_BASE, Genode::Board_base::GPIO5_MMIO_SIZE,
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Genode::Board_base::GPIO5_IRQ),
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_gpio_bank_5(_ep, Genode::Board_base::GPIO6_MMIO_BASE, Genode::Board_base::GPIO6_MMIO_SIZE,
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Genode::Board_base::GPIO6_IRQ)
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{
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for (int i = 0; i < MAX_BANKS; ++i) {
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if (verbose)
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PDBG("GPIO%d ctrl=%08x",
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i+1, _gpio_bank(i << PIN_SHIFT)->regs()->read<Gpio_reg::Ctrl>());
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}
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}
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public:
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static Omap4_driver& factory(Server::Entrypoint &ep);
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/******************************
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** Gpio::Driver interface **
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******************************/
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void direction(unsigned gpio, bool input)
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{
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if (verbose) PDBG("gpio=%d input=%d", gpio, input);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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gpio_reg->write<Gpio_reg::Oe>(input ? 1 : 0, _gpio_index(gpio));
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}
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void write(unsigned gpio, bool level)
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{
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if (verbose) PDBG("gpio=%d level=%d", gpio, level);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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if (level)
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gpio_reg->write<Gpio_reg::Setdataout>(1 << _gpio_index(gpio));
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else
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gpio_reg->write<Gpio_reg::Cleardataout>(1 << _gpio_index(gpio));
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}
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bool read(unsigned gpio)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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return gpio_reg->read<Gpio_reg::Datain>(_gpio_index(gpio));
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}
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void debounce_enable(unsigned gpio, bool enable)
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{
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if (verbose) PDBG("gpio=%d enable=%d", gpio, enable);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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gpio_reg->write<Gpio_reg::Debounceenable>(enable ? 1 : 0,
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_gpio_index(gpio));
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}
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void debounce_time(unsigned gpio, unsigned long us)
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{
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if (verbose) PDBG("gpio=%d us=%ld", gpio, us);
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unsigned char debounce;
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if (us < 32)
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debounce = 0x01;
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else if (us > 7936)
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debounce = 0xff;
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else
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debounce = (us / 0x1f) - 1;
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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gpio_reg->write<Gpio_reg::Debouncingtime::Time>(debounce);
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}
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void falling_detect(unsigned gpio)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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gpio_reg->write<Gpio_reg::Leveldetect0> (0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Leveldetect1> (0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Fallingdetect>(1, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Risingdetect> (0, _gpio_index(gpio));
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}
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void rising_detect(unsigned gpio)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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gpio_reg->write<Gpio_reg::Leveldetect0> (0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Leveldetect1> (0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Fallingdetect>(0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Risingdetect> (1, _gpio_index(gpio));
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}
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void high_detect(unsigned gpio)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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gpio_reg->write<Gpio_reg::Leveldetect0> (0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Leveldetect1> (1, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Fallingdetect>(0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Risingdetect> (0, _gpio_index(gpio));
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}
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void low_detect(unsigned gpio)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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Gpio_reg *gpio_reg = _gpio_bank(gpio)->regs();
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gpio_reg->write<Gpio_reg::Leveldetect0> (1, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Leveldetect1> (0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Fallingdetect>(0, _gpio_index(gpio));
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gpio_reg->write<Gpio_reg::Risingdetect> (0, _gpio_index(gpio));
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}
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void irq_enable(unsigned gpio, bool enable)
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{
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if (verbose) PDBG("gpio=%d enable=%d", gpio, enable);
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_gpio_bank(gpio)->irq(_gpio_index(gpio), enable);
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}
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void ack_irq(unsigned gpio)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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_gpio_bank(gpio)->ack_irq(_gpio_index(gpio));
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}
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void register_signal(unsigned gpio,
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Genode::Signal_context_capability cap)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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_gpio_bank(gpio)->sigh(_gpio_index(gpio), cap); }
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void unregister_signal(unsigned gpio)
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{
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if (verbose) PDBG("gpio=%d", gpio);
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Genode::Signal_context_capability cap;
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_gpio_bank(gpio)->sigh(_gpio_index(gpio), cap);
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}
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bool gpio_valid(unsigned gpio) { return gpio < (MAX_PINS*MAX_BANKS); }
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};
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Omap4_driver& Omap4_driver::factory(Server::Entrypoint &ep)
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{
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static Omap4_driver driver(ep);
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return driver;
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}
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#endif /* _DRIVER_H_ */
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