3df03fbc41
The old implementation cleared all other bits in the SCU control register when enabling the SCU, which broke the kernel startup on zynq- based boards. By only raising the enable bit, we can keep the initial/default state e.g. as set up by uboot. Fixes #1953
72 lines
1.3 KiB
C++
72 lines
1.3 KiB
C++
/*
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* \brief Snoop control unit
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* \author Martin Stein
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* \author Stefan Kalkowski
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* \date 2015-12-15
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*/
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/*
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* Copyright (C) 2015-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* Genode includes */
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#include <util/mmio.h>
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/* local includes */
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#include <board.h>
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namespace Genode {
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class Scu;
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}
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class Genode::Scu : Genode::Mmio
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{
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private:
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struct Cr : Register<0x0, 32>
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{
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struct Enable : Bitfield<0, 1> { };
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};
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struct Dcr : Register<0x30, 32>
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{
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struct Bit_0 : Bitfield<0, 1> { };
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};
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struct Iassr : Register<0xc, 32>
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{
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struct Cpu0_way : Bitfield<0, 4> { };
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struct Cpu1_way : Bitfield<4, 4> { };
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struct Cpu2_way : Bitfield<8, 4> { };
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struct Cpu3_way : Bitfield<12, 4> { };
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};
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Board &_board;
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public:
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Scu(Board & board) : Mmio(Board::SCU_MMIO_BASE), _board(board) { }
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void invalidate()
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{
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Iassr::access_t iassr = 0;
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for (Iassr::access_t way = 0; way <= Iassr::Cpu0_way::mask();
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way++) {
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Iassr::Cpu0_way::set(iassr, way);
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Iassr::Cpu1_way::set(iassr, way);
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Iassr::Cpu2_way::set(iassr, way);
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Iassr::Cpu3_way::set(iassr, way);
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write<Iassr>(iassr);
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}
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}
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void enable()
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{
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if (_board.errata(Board::ARM_764369)) write<Dcr::Bit_0>(1);
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write<Cr::Enable>(1);
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}
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};
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