129 lines
3.0 KiB
C++
129 lines
3.0 KiB
C++
/*
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* \brief Cpu class implementation specific to Cortex A9 SMP
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* \author Stefan Kalkowski
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* \date 2015-12-09
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*/
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/*
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* Copyright (C) 2015-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <kernel/lock.h>
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#include <kernel/pd.h>
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#include <pic.h>
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#include <scu.h>
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#include <board.h>
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/* base-hw includes */
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#include <kernel/perf_counter.h>
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using namespace Kernel;
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/* entrypoint for non-boot CPUs */
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extern "C" void * _start_secondary_cpus;
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/**
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* SMP-safe simple counter
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*/
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class Counter
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{
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private:
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Kernel::Lock _lock;
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volatile int _value = 0;
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public:
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void inc()
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{
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Kernel::Lock::Guard guard(_lock);
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Genode::memory_barrier();
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_value++;
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}
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void wait_for(int const v) {
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while (_value < v) ; }
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};
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static volatile bool primary_cpu = true; /* indicates boot cpu status */
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static Counter data_cache_invalidated; /* counts cpus that invalidated
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their data cache */
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static Counter data_cache_enabled; /* counts cpus that enabled
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their data cache */
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static Counter smp_coherency_enabled; /* counts cpus that enabled
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their SCU */
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/*
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* The initialization of Cortex A9 multicore systems implies a sophisticated
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* algorithm in early revisions of this cpu.
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*
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* See ARM's Cortex-A9 MPCore TRM r2p0 in section 5.3.5 for more details
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*/
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void Kernel::Cpu::init(Kernel::Pic &pic, Kernel::Pd & core_pd, Genode::Board & board)
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{
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bool primary = primary_cpu;
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if (primary) primary_cpu = false;
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Sctlr::init();
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Psr::write(Psr::init_kernel());
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/* locally initialize interrupt controller */
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pic.init_cpu_local();
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invalidate_inner_data_cache();
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data_cache_invalidated.inc();
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/* primary cpu wakes up all others */
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if (primary && NR_OF_CPUS > 1)
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board.wake_up_all_cpus(&_start_secondary_cpus);
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/* wait for other cores' data cache invalidation */
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data_cache_invalidated.wait_for(NR_OF_CPUS);
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if (primary) {
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Genode::Scu scu(board);
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scu.invalidate();
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board.l2_cache().invalidate();
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scu.enable();
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}
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/* secondary cpus wait for the primary's cache activation */
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if (!primary) data_cache_enabled.wait_for(1);
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enable_mmu_and_caches(core_pd);
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data_cache_enabled.inc();
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clean_invalidate_inner_data_cache();
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/* wait for other cores' data cache activation */
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data_cache_enabled.wait_for(NR_OF_CPUS);
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if (primary) board.l2_cache().enable();
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/* secondary cpus wait for the primary's coherency activation */
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if (!primary) smp_coherency_enabled.wait_for(1);
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Actlr::enable_smp();
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smp_coherency_enabled.inc();
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/* wait for other cores' coherency activation */
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smp_coherency_enabled.wait_for(NR_OF_CPUS);
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init_advanced_fp_simd();
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{
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Lock::Guard guard(data_lock());
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/* enable performance counter */
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perf_counter()->enable();
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/* enable timer interrupt */
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pic.unmask(Timer::interrupt_id(id()), id());
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}
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}
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