56 lines
1.5 KiB
C++
56 lines
1.5 KiB
C++
/*
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* \brief CPU driver for core
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* \author Norman Feske
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2012-08-30
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*/
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/*
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* Copyright (C) 2012-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <cpu.h>
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#include <kernel/pd.h>
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#include <kernel/kernel.h>
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void Genode::Arm::clean_invalidate_data_cache() {
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asm volatile ("mcr p15, 0, %[rd], c7, c14, 0" :: [rd]"r"(0) : ); }
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void Genode::Arm::enable_mmu_and_caches(Kernel::Pd& pd)
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{
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/* check for mapping restrictions */
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assert(!Cpu::restricted_page_mappings());
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invalidate_tlb();
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Cidr::write(pd.asid);
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Dacr::write(Dacr::init_virt_kernel());
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Ttbr0::write(Ttbr0::init((Genode::addr_t)pd.translation_table()));
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Ttbcr::write(0);
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Sctlr::enable_mmu_and_caches();
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}
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void Genode::Cpu::translation_added(Genode::addr_t const addr,
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Genode::size_t const size)
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{
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using namespace Kernel;
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/*
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* The Cortex-A8 CPU can't use the L1 cache on page-table
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* walks. Therefore, as the page-tables lie in write-back cacheable
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* memory we've to clean the corresponding cache-lines even when a
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* page table entry is added. We only do this as core as the kernel
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* adds translations solely before MMU and caches are enabled.
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*/
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if (is_user()) update_data_region(addr, size);
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else {
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Cpu * const cpu = cpu_pool()->cpu(Cpu::executing_id());
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cpu->clean_invalidate_data_cache();
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}
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}
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