7aff1895bf
This commit enables multi-processing for all Cortex A9 SoCs we currently support. Moreover, it thereby enables the L2 cache for i.MX6 that was not enabled until now. However, the QEMU variants hw_pbxa9 and hw_zynq still only use 1 core, because the busy cpu synchronization used when initializing multiple Cortex A9 cores leads to horrible boot times on QEMU. During this work the CPU initialization in general was reworked. From now on lots of hardware specifics were put into the 'spec' specific files, some generic hook functions and abstractions thereby were eliminated. This results to more lean implementations for instance on non-SMP platforms, or in the x86 case where cache maintainance is a non-issue. Due to the fact that memory/cache coherency and SMP are closely coupled on ARM Cortex A9 this commit combines so different aspects. Fix #1312 Fix #1807 |
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README
This is generic part of the Genode implementation. It consists of two parts: :_Core_: is the ultimate root of the Genode application tree and provides abstractions for the lowest-level hardware resources such as RAM, ROM, CPU, and generic device access. All generic parts of Core can be found here - for system-specific implementations refer to the appropriate 'base-<system>' directory. :_Base libraries and protocols_: that are used by each Genode component to interact with other components. This is the glue that holds everything together.