76bc2b9e89
Fix #2393
47 lines
1.0 KiB
C++
47 lines
1.0 KiB
C++
/*
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* \brief Programmable interrupt controller for core
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* \author Sebastian Sumpf
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* \date 2015-06-02
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*
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* There currently is no interrupt controller defined for the RISC-V platform.
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__RISCV__PIC_H_
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#define _CORE__SPEC__RISCV__PIC_H_
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namespace Genode { class Pic; }
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/**
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* Dummy PIC driver for core
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*/
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class Genode::Pic
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{
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public:
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enum {
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/*
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* FIXME: dummy ipi value on non-SMP platform, should be removed
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* when SMP is an aspect of CPUs only compiled where necessary
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*/
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IPI = 0,
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NR_OF_IRQ = 15,
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};
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Pic() { }
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bool take_request(unsigned & i) { i = 0; return true; }
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void unmask(unsigned const i, unsigned) { }
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void mask(unsigned const i) { }
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void finish_request() { }
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};
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namespace Kernel { class Pic : public Genode::Pic { }; }
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#endif /* _CORE__SPEC__RISCV__PIC_H_ */
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