6d48b5484d
This commit fixes the following issues regarding cache maintainance under ARM: * read out I-, and D-cache line size at runtime and use the correct one * remove 'update_data_region' call from unprivileged syscalls * rename 'update_instr_region' syscall to 'cache_coherent_region' to reflect what it doing, namely make I-, and D-cache coherent * restrict 'cache_coherent_region' syscall to one page at a time * lookup the region given in a 'cache_coherent_region' syscall in the page-table of the PD to prevent machine exceptions in the kernel * only clean D-cache lines, do not invalidate them when pages where added on Cortex-A8 and ARMv6 (MMU sees phys. memory here) * remove unused code relicts of cache maintainance In addition it introduces per architecture memory clearance functions used by core, when preparing new dataspaces. Thereby, it optimizes: * on ARMv7 using per-word assignments * on ARMv8 using cacheline zeroing * on x86_64 using 'rept stosq' assembler instruction Fix #3685
78 lines
1.6 KiB
C++
78 lines
1.6 KiB
C++
/*
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* \brief Driver for the Versatile Express A9X4 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__PLATFORM__VEA9X4__DRIVERS__BOARD_BASE_H_
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#define _INCLUDE__PLATFORM__VEA9X4__DRIVERS__BOARD_BASE_H_
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namespace Vea9x4 { struct Board; }
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/**
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* Driver for the Versatile Express A9X4 board
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*
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* Implies the uATX motherboard and the CoreTile Express A9X4 daughterboard
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*/
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struct Vea9x4::Board
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{
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enum
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{
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/* MMIO */
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MMIO_0_BASE = 0x10000000,
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MMIO_0_SIZE = 0x10000000,
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MMIO_1_BASE = 0x4C000000,
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MMIO_1_SIZE = 0x04000000,
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/* RAM */
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RAM_0_BASE = 0x60000000,
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RAM_0_SIZE = 0x20000000,
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RAM_1_BASE = 0x84000000,
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RAM_1_SIZE = 0x1c000000,
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RAM_2_BASE = 0x48000000,
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RAM_2_SIZE = 0x02000000,
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/* UART */
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PL011_0_MMIO_BASE = MMIO_0_BASE + 0x9000,
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PL011_0_MMIO_SIZE = 0x1000,
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PL011_0_CLOCK = 24*1000*1000,
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PL011_0_IRQ = 37,
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PL011_1_IRQ = 38,
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PL011_2_IRQ = 39,
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PL011_3_IRQ = 40,
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/* timer/counter */
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SP804_0_1_MMIO_BASE = MMIO_0_BASE + 0x11000,
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SP804_0_1_MMIO_SIZE = 0x1000,
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SP804_0_1_CLOCK = 1000*1000,
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SP804_0_1_IRQ = 34,
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/* PS2 */
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KMI_0_IRQ = 44,
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KMI_1_IRQ = 45,
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/* LAN */
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LAN9118_IRQ = 47,
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/* card reader */
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PL180_0_IRQ = 9,
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PL180_1_IRQ = 10,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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CORTEX_A9_PRIVATE_TIMER_CLK = 200010000,
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};
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};
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#endif /* _INCLUDE__PLATFORM__VEA9X4__DRIVERS__BOARD_BASE_H_ */
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