223 lines
6.2 KiB
C++
223 lines
6.2 KiB
C++
/*
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* \brief Driver for the Central Security Unit
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* \author Stefan Kalkowski
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* \date 2012-11-06
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*/
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/*
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* Copyright (C) 2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _SRC__SERVER__VMM__INCLUDE__CSU_H_
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#define _SRC__SERVER__VMM__INCLUDE__CSU_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <util/register.h>
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namespace Genode
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{
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class Csu : Mmio
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{
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private:
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template <off_t OFF>
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struct Csl : public Register<OFF, 32>
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{
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enum {
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SECURE = 0x33,
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UNSECURE = 0xff,
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};
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struct Slave_a : Register<OFF, 32>::template Bitfield<0, 9> { };
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struct Slave_b : Register<OFF, 32>::template Bitfield<16, 9> { };
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};
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struct Master : public Register<0x218, 32>
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{
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enum {
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SECURE_UNLOCKED,
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SECURE_LOCKED,
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UNSECURE_UNLOCKED,
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UNSECURE_LOCKED
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};
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struct Esdhc3 : Bitfield<0,2> { };
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struct Cortex : Bitfield<2,2> { };
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struct Sdma : Bitfield<4,2> { };
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struct Gpu : Bitfield<6,2> { };
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struct Usb : Bitfield<8,2> { };
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struct Pata : Bitfield<10,2> { };
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struct Mlb : Bitfield<14,2> { };
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struct Rtic : Bitfield<18,2> { };
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struct Esdhc4 : Bitfield<20,2> { };
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struct Fec : Bitfield<22,2> { };
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struct Dap : Bitfield<24,2> { };
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struct Esdhc1 : Bitfield<26,2> { };
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struct Esdhc2 : Bitfield<28,2> { };
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};
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struct Alarm_mask : public Register<0x230, 32> { };
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struct Irq_ctrl : public Register<0x368, 32> { };
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public:
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typedef Csl<0x00> Csl00;
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typedef Csl<0x04> Csl01;
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typedef Csl<0x08> Csl02;
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typedef Csl<0x0c> Csl03;
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typedef Csl<0x10> Csl04;
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typedef Csl<0x14> Csl05;
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typedef Csl<0x18> Csl06;
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typedef Csl<0x1c> Csl07;
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typedef Csl<0x20> Csl08;
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typedef Csl<0x24> Csl09;
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typedef Csl<0x28> Csl10;
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typedef Csl<0x2c> Csl11;
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typedef Csl<0x30> Csl12;
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typedef Csl<0x34> Csl13;
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typedef Csl<0x38> Csl14;
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typedef Csl<0x3c> Csl15;
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typedef Csl<0x40> Csl16;
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typedef Csl<0x44> Csl17;
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typedef Csl<0x48> Csl18;
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typedef Csl<0x4c> Csl19;
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typedef Csl<0x50> Csl20;
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typedef Csl<0x54> Csl21;
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typedef Csl<0x58> Csl22;
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typedef Csl<0x5c> Csl23;
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typedef Csl<0x60> Csl24;
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typedef Csl<0x64> Csl25;
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typedef Csl<0x68> Csl26;
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typedef Csl<0x6c> Csl27;
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typedef Csl<0x70> Csl28;
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typedef Csl<0x74> Csl29;
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typedef Csl<0x78> Csl30;
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typedef Csl<0x7c> Csl31;
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Csu(addr_t const base) : Mmio(base)
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{
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/* Power (CCM, SRC, DPLLIP1-4, GPC and OWIRE) */
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write<Csl09::Slave_a>(Csl00::UNSECURE);
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/* AHBMAX S0-S2 */
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write<Csl09::Slave_b>(Csl00::UNSECURE);
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write<Csl20::Slave_a>(Csl00::UNSECURE);
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write<Csl06::Slave_b>(Csl00::UNSECURE);
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/* AHBMAX M6 */
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write<Csl10::Slave_a>(Csl00::UNSECURE);
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/* Timer (EPIT, GPT) TODO */
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write<Csl04::Slave_a>(Csl00::UNSECURE);
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/* UART 1-5 */
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write<Csl07::Slave_b>(Csl00::UNSECURE);
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write<Csl08::Slave_a>(Csl00::UNSECURE);
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write<Csl26::Slave_a>(Csl00::UNSECURE);
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write<Csl30::Slave_b>(Csl00::UNSECURE);
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write<Csl19::Slave_a>(Csl00::UNSECURE);
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/* GPIO */
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//write<Csl00::Slave_b>(Csl00::UNSECURE);
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//write<Csl01::Slave_a>(Csl00::UNSECURE);
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//write<Csl01::Slave_b>(Csl00::UNSECURE);
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//write<Csl02::Slave_a>(Csl00::UNSECURE);
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/* IOMUXC TODO */
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write<Csl05::Slave_a>(Csl00::UNSECURE);
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/* SDMA TODO */
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write<Csl15::Slave_a>(Csl00::UNSECURE);
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/* USB */
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write<Csl00::Slave_a>(Csl00::UNSECURE);
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/* TVE */
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//write<Csl22::Slave_b>(Csl00::UNSECURE);
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/* I2C */
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//write<Csl18::Slave_a>(Csl00::UNSECURE);
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//write<Csl17::Slave_b>(Csl00::UNSECURE);
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//write<Csl31::Slave_a>(Csl00::UNSECURE);
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/* IPU */
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//write<Csl24::Slave_a>(Csl00::UNSECURE);
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/* Audio */
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write<Csl18::Slave_b>(Csl00::UNSECURE);
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/* SATA */
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write<Csl07::Slave_a>(Csl00::UNSECURE);
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/* FEC */
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write<Csl22::Slave_a>(Csl00::UNSECURE);
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/* SDHCI 1-4 */
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write<Csl25::Slave_a>(Csl00::UNSECURE);
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write<Csl25::Slave_b>(Csl00::UNSECURE);
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write<Csl28::Slave_a>(Csl00::UNSECURE);
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write<Csl28::Slave_b>(Csl00::UNSECURE);
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/* SPDIF */
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write<Csl29::Slave_a>(Csl00::UNSECURE);
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/* GPU 2D */
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write<Csl24::Slave_b>(Csl00::UNSECURE);
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/* GPU 3D */
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write<Csl27::Slave_b>(Csl00::UNSECURE);
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write<Csl02::Slave_b>(Csl00::UNSECURE);
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write<Csl03::Slave_a>(Csl00::UNSECURE);
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write<Csl03::Slave_b>(Csl00::UNSECURE);
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write<Csl04::Slave_b>(Csl00::UNSECURE); // SRTC
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write<Csl05::Slave_b>(Csl00::UNSECURE);
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write<Csl06::Slave_a>(Csl00::UNSECURE);
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write<Csl08::Slave_b>(Csl00::UNSECURE);
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write<Csl10::Slave_b>(Csl00::UNSECURE);
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write<Csl11::Slave_a>(Csl00::UNSECURE);
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write<Csl11::Slave_b>(Csl00::UNSECURE);
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write<Csl12::Slave_a>(Csl00::UNSECURE);
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write<Csl12::Slave_b>(Csl00::UNSECURE);
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write<Csl13::Slave_a>(Csl00::UNSECURE);
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write<Csl13::Slave_b>(Csl00::UNSECURE);
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write<Csl14::Slave_a>(Csl00::UNSECURE);
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write<Csl14::Slave_b>(Csl00::UNSECURE);
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write<Csl15::Slave_b>(Csl00::UNSECURE); // SCC
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write<Csl16::Slave_a>(Csl00::UNSECURE);
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write<Csl16::Slave_b>(Csl00::UNSECURE); // RTIC
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write<Csl17::Slave_a>(Csl00::UNSECURE);
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write<Csl19::Slave_b>(Csl00::UNSECURE);
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write<Csl20::Slave_b>(Csl00::UNSECURE);
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write<Csl21::Slave_a>(Csl00::UNSECURE);
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write<Csl21::Slave_b>(Csl00::UNSECURE);
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//write<Csl23::Slave_a>(Csl00::UNSECURE); //VPU
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write<Csl23::Slave_b>(Csl00::UNSECURE);
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write<Csl26::Slave_b>(Csl00::UNSECURE);
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write<Csl27::Slave_a>(Csl00::UNSECURE);
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write<Csl29::Slave_b>(Csl00::UNSECURE);
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write<Csl30::Slave_a>(Csl00::UNSECURE);
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write<Csl31::Slave_b>(Csl00::UNSECURE);
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write<Master::Sdma>(Master::UNSECURE_UNLOCKED);
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write<Master::Esdhc3>(Master::UNSECURE_UNLOCKED);
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write<Master::Gpu>(Master::UNSECURE_UNLOCKED);
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write<Master::Usb>(Master::UNSECURE_UNLOCKED);
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write<Master::Pata>(Master::UNSECURE_UNLOCKED);
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write<Master::Esdhc4>(Master::UNSECURE_UNLOCKED);
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write<Master::Fec>(Master::UNSECURE_UNLOCKED);
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write<Master::Dap>(Master::UNSECURE_UNLOCKED);
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write<Master::Esdhc1>(Master::UNSECURE_UNLOCKED);
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write<Master::Esdhc2>(Master::UNSECURE_UNLOCKED);
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}
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};
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}
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#endif /* _BASE_HW__SRC__SERVER__VMM__TSC_380_H_ */
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