da17f2cbd3
Since gcc 8.3.0 generates SSE instructions into kernel code, the kernel itself may raise FPU exceptions and/or corrupt user level FPU contexts thereby. Both things are not feasible, and therefore, lazy FPU switching becomes a no go for base-hw because we cannot avoid FPU instructions because of the entanglement of base-hw, base, and the tool chain (libgcc_eh.a). issue #3365
65 lines
1.3 KiB
C++
65 lines
1.3 KiB
C++
/*
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* \brief x86_64 FPU context
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* \author Sebastian Sumpf
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* \date 2019-05-23
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*/
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/*
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* Copyright (C) 2019 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__X86_64__FPU_H_
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#define _CORE__SPEC__X86_64__FPU_H_
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/* Genode includes */
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#include <util/misc_math.h>
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#include <util/mmio.h>
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#include <util/string.h>
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namespace Genode { class Fpu_context; }
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class Genode::Fpu_context
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{
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addr_t _fxsave_addr { 0 };
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/*
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* FXSAVE area providing storage for x87 FPU, MMX, XMM,
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* and MXCSR registers.
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*
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* For further details see Intel SDM Vol. 2A,
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* 'FXSAVE instruction'.
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*/
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char _fxsave_area[527];
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struct Context : Mmio
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{
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struct Fcw : Register<0, 16> { };
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struct Mxcsr : Register<24, 32> { };
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Context(addr_t const base) : Mmio(base)
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{
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memset((void *)base, 0, 512);
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write<Fcw>(0x37f); /* mask exceptions SysV ABI */
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write<Mxcsr>(0x1f80);
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}
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};
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public:
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Fpu_context()
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{
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/* align to 16 byte boundary */
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_fxsave_addr = align_addr((addr_t)_fxsave_area, 4);
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/* set fcw/mxcsr */
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Context init(_fxsave_addr);
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}
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addr_t fpu_context() const { return _fxsave_addr; }
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};
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#endif /* _CORE__SPEC__X86_64__FPU_H_ */
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