87 lines
1.8 KiB
C++
87 lines
1.8 KiB
C++
/*
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* \brief CPU driver for core
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* \author Sebastian Sumpf
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* \date 2015-06-02
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__RISCV__CPU_H_
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#define _CORE__SPEC__RISCV__CPU_H_
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/* Genode includes */
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#include <base/stdint.h>
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#include <cpu/cpu_state.h>
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#include <util/register.h>
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#include <base/internal/align_at.h>
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#include <kernel/interface.h>
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#include <hw/spec/riscv/cpu.h>
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namespace Kernel { struct Thread_fault; }
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namespace Genode
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{
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/**
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* CPU driver for core
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*/
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class Cpu;
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typedef __uint128_t sizet_arithm_t;
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}
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namespace Kernel { class Pd; }
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class Genode::Cpu : public Hw::Riscv_cpu
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{
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public:
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struct alignas(8) Context : Cpu_state
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{
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Context(bool);
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};
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struct Mmu_context
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{
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Sptbr::access_t sptbr = 0;
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Mmu_context(addr_t page_table_base);
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~Mmu_context();
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};
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/**
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* From the manual
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*
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* The behavior of SFENCE.VM depends on the current value of the sasid
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* register. If sasid is nonzero, SFENCE.VM takes effect only for address
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* translations in the current address space. If sasid is zero, SFENCE.VM
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* affects address translations for all address spaces. In this case, it
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* also affects global mappings, which are described in Section 4.5.1.
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*
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* Right no we will flush anything
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*/
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static void sfence()
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{
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/*
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* Note: In core the address space id must be zero
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*/
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asm volatile ("sfence.vm\n");
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}
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static void invalidate_tlb_by_pid(unsigned const /* pid */) { sfence(); }
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void switch_to(Mmu_context & context);
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static void mmu_fault(Context & c, Kernel::Thread_fault & f);
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static unsigned executing_id() { return 0; }
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};
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#endif /* _CORE__SPEC__RISCV__CPU_H_ */
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