125 lines
2.9 KiB
C++
125 lines
2.9 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \author Stefan Kalkowski
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__CORTEX_A15__CPU_H_
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#define _CORE__SPEC__CORTEX_A15__CPU_H_
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/* core includes */
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#include <spec/arm_v7/cpu_support.h>
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namespace Genode { class Cpu; }
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class Genode::Cpu : public Arm_v7_cpu
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{
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public:
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/*********************************
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** Virtualization extensions **
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*********************************/
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/**
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* Hypervisor system trap register
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*/
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struct Hstr : Register<32>
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{
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/* System coprocessor primary register access trap */
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template <unsigned R>
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struct T : Bitfield<R, 1> {};
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static access_t init()
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{
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/*
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* allow cache (7), TLB (8) maintenance, and performance
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* monitor (9), process/thread ID register (13) and timer (14)
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* access.
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*/
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access_t v = 0;
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T<0>::set(v, 1);
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T<1>::set(v, 1);
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T<2>::set(v, 1);
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T<3>::set(v, 1);
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T<5>::set(v, 1);
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T<6>::set(v, 1);
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T<10>::set(v, 1);
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T<11>::set(v, 1);
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T<12>::set(v, 1);
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T<15>::set(v, 1);
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return v;
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};
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};
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/**
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* Hypervisor control register
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*/
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struct Hcr : Register<32>
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{
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struct Vm : Bitfield<0, 1> {}; /* VT MMU enabled */
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struct Fmo : Bitfield<3, 1> {}; /* FIQ cannot been masked */
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struct Imo : Bitfield<4, 1> {}; /* IRQ cannot been masked */
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struct Amo : Bitfield<5, 1> {}; /* A bit cannot been masked */
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struct Twi : Bitfield<13, 1> {}; /* trap on WFI instruction */
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struct Twe : Bitfield<14, 1> {}; /* trap on WFE instruction */
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struct Tidcp : Bitfield<20, 1> {}; /* trap lockdown */
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struct Tac : Bitfield<21, 1> {}; /* trap ACTLR accesses */
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struct Tvm : Bitfield<26, 1> {}; /* trap virtual memory ctrls */
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static access_t init()
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{
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access_t v = 0;
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Vm::set(v, 1);
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Fmo::set(v, 1);
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Imo::set(v, 1);
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Amo::set(v, 1);
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Twi::set(v, 1);
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Twe::set(v, 1);
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Tidcp::set(v, 1);
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Tac::set(v, 1);
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Tvm::set(v, 1);
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return v;
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};
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};
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/**
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* An usermode execution state
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*/
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struct Mmu_context
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{
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Ttbr_64bit::access_t ttbr0;
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Mmu_context(addr_t const table);
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~Mmu_context();
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Genode::uint8_t id() const { return Ttbr_64bit::Asid::get(ttbr0); }
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};
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static void mmu_fault_status(Fsr::access_t fsr,
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Kernel::Thread_fault & fault);
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id() { return Mpidr::Aff_0::get(Mpidr::read()); }
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void switch_to(Context &, Mmu_context & mmu_context)
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{
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if (mmu_context.id() && (Ttbr0_64bit::read() != mmu_context.ttbr0))
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Ttbr0_64bit::write(mmu_context.ttbr0);
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}
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};
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#endif /* _CORE__SPEC__CORTEX_A15__CPU_H_ */
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