96 lines
2.3 KiB
C++
96 lines
2.3 KiB
C++
/*
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* \brief Platform implementations specific for base-hw and VEA9X4
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* \author Martin Stein
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* \date 2012-04-27
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <drivers/trustzone.h>
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/* core includes */
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#include <board.h>
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#include <processor_driver.h>
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#include <platform.h>
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#include <pic/vea9x4_trustzone.h>
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#include <trustzone.h>
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#include <pic.h>
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using namespace Genode;
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/* monitor exception vector address */
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extern int _mon_kernel_entry;
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void Kernel::init_trustzone(Pic * pic)
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{
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/* check for compatibility */
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if (PROCESSORS > 1) {
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PERR("trustzone not supported with multiprocessing");
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return;
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}
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/* set exception vector entry */
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Processor_driver::mon_exception_entry_at((Genode::addr_t)&_mon_kernel_entry);
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/* enable coprocessor access for TZ VMs */
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Processor_driver::allow_coprocessor_nonsecure();
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/* set unsecure IRQs */
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pic->unsecure(34); //Timer 0/1
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pic->unsecure(35); //Timer 2/3
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pic->unsecure(36); //RTC
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pic->unsecure(37); //UART0
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pic->unsecure(41); //MCI0
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pic->unsecure(42); //MCI1
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pic->unsecure(43); //AACI
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pic->unsecure(44); //KMI0
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pic->unsecure(45); //KMI1
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pic->unsecure(47); //ETHERNET
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pic->unsecure(48); //USB
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}
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Native_region * Platform::_ram_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Trustzone::SECURE_RAM_BASE, Trustzone::SECURE_RAM_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
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{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
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{ Trustzone::NONSECURE_RAM_BASE, Trustzone::NONSECURE_RAM_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/* Core timer and PIC */
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{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
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Board::CORTEX_A9_PRIVATE_MEM_SIZE },
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/* Core UART */
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{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Processor_driver::User_context::User_context() { cpsr = Psr::init_user_with_trustzone(); }
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