6a3368ee27
fix #1006
340 lines
9.4 KiB
C++
340 lines
9.4 KiB
C++
/*
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* \brief Singlethreaded minimalistic kernel
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* \author Martin Stein
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* \date 2011-10-20
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*
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* This kernel is the only code except the mode transition PIC, that runs in
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* privileged CPU mode. It has two tasks. First it initializes the process
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* 'core', enriches it with the whole identically mapped address range,
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* joins and applies it, assigns one thread to it with a userdefined
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* entrypoint (the core main thread) and starts this thread in userland.
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* Afterwards it is called each time an exception occurs in userland to do
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* a minimum of appropriate exception handling. Thus it holds a CPU context
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* for itself as for any other thread. But due to the fact that it never
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* relies on prior kernel runs this context only holds some constant pointers
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* such as SP and IP.
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <kernel/pd.h>
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#include <kernel/vm.h>
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#include <kernel/irq.h>
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#include <platform_pd.h>
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#include <trustzone.h>
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#include <timer.h>
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#include <pic.h>
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/* base includes */
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#include <unmanaged_singleton.h>
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/* base-hw includes */
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#include <kernel/perf_counter.h>
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using namespace Kernel;
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extern Genode::Native_thread_id _main_thread_id;
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extern "C" void CORE_MAIN();
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extern void * _start_secondary_processors;
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Genode::Native_utcb * _main_thread_utcb;
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namespace Kernel
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{
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/**
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* Return interrupt-controller singleton
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*/
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Pic * pic() { return unmanaged_singleton<Pic>(); }
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/* import Genode types */
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typedef Genode::umword_t umword_t;
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typedef Genode::Core_tlb Core_tlb;
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typedef Genode::Core_thread_id Core_thread_id;
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void init_platform();
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}
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namespace Kernel
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{
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Pd_ids * pd_ids() { return unmanaged_singleton<Pd_ids>(); }
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Thread_ids * thread_ids() { return unmanaged_singleton<Thread_ids>(); }
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Signal_context_ids * signal_context_ids() { return unmanaged_singleton<Signal_context_ids>(); }
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Signal_receiver_ids * signal_receiver_ids() { return unmanaged_singleton<Signal_receiver_ids>(); }
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Pd_pool * pd_pool() { return unmanaged_singleton<Pd_pool>(); }
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Thread_pool * thread_pool() { return unmanaged_singleton<Thread_pool>(); }
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Signal_context_pool * signal_context_pool() { return unmanaged_singleton<Signal_context_pool>(); }
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Signal_receiver_pool * signal_receiver_pool() { return unmanaged_singleton<Signal_receiver_pool>(); }
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/**
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* Return singleton kernel-timer
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*/
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Timer * timer()
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{
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static Timer _object;
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return &_object;
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}
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/**
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* Start a new scheduling lap
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*/
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void reset_lap_time(unsigned const processor_id)
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{
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unsigned const tics = timer()->ms_to_tics(USER_LAP_TIME_MS);
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timer()->start_one_shot(tics, processor_id);
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}
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/**
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* Static kernel PD that describes core
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*/
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static Pd * core()
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{
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/**
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* Core protection-domain
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*/
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class Core_pd : public Pd
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{
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public:
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/**
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* Constructor
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*/
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Core_pd(Tlb * const tlb, Platform_pd * const platform_pd)
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:
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Pd(tlb, platform_pd)
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{ }
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};
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constexpr int tlb_align = 1 << Core_tlb::ALIGNM_LOG2;
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Core_tlb * core_tlb = unmanaged_singleton<Core_tlb, tlb_align>();
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Core_pd * core_pd = unmanaged_singleton<Core_pd>(core_tlb, nullptr);
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return core_pd;
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}
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/**
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* Get core attributes
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*/
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unsigned core_id() { return core()->id(); }
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}
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namespace Kernel
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{
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/**
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* Get attributes of the mode transition region in every PD
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*/
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addr_t mode_transition_virt_base() { return mtc()->VIRT_BASE; }
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size_t mode_transition_size() { return mtc()->SIZE; }
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/**
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* Get attributes of the kernel objects
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*/
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size_t thread_size() { return sizeof(Thread); }
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size_t pd_size() { return sizeof(Tlb) + sizeof(Pd); }
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size_t signal_context_size() { return sizeof(Signal_context); }
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size_t signal_receiver_size() { return sizeof(Signal_receiver); }
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unsigned pd_alignm_log2() { return Tlb::ALIGNM_LOG2; }
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size_t vm_size() { return sizeof(Vm); }
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enum { STACK_SIZE = 64 * 1024 };
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/**
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* Return lock that guards all kernel data against concurrent access
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*/
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Lock & data_lock()
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{
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static Lock s;
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return s;
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}
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addr_t core_tlb_base;
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unsigned core_pd_id;
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/**
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* Handle interrupt request
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*
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* \param processor kernel object of targeted processor
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* \param processor_id kernel name of targeted processor
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*/
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void handle_interrupt(Processor * const processor,
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unsigned const processor_id)
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{
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/* determine handling for specific interrupt */
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unsigned irq_id;
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if (pic()->take_request(irq_id))
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{
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/* check wether the interrupt is a scheduling timeout */
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if (timer()->interrupt_id(processor_id) == irq_id)
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{
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/* handle scheduling timeout */
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processor->scheduler()->yield();
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timer()->clear_interrupt(processor_id);
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reset_lap_time(processor_id);
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} else {
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/* try to inform the user interrupt-handler */
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Irq::occurred(irq_id);
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}
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}
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/* end interrupt request at controller */
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pic()->finish_request();
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}
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}
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/**
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* Enable kernel-entry assembly to get an exclusive stack at every processor
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*/
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char kernel_stack[PROCESSORS][Kernel::STACK_SIZE] __attribute__((aligned()));
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unsigned kernel_stack_size = Kernel::STACK_SIZE;
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/**
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* Setup kernel enviroment before activating secondary processors
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*/
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extern "C" void init_kernel_uniprocessor()
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{
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/************************************************************************
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** As atomic operations are broken in physical mode on some platforms **
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** we must avoid the use of 'cmpxchg' by now (includes not using any **
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** local static objects. **
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************************************************************************/
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/* calculate in advance as needed later when data writes aren't allowed */
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core_tlb_base = core()->tlb()->base();
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core_pd_id = core_id();
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/* initialize all processor objects */
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multiprocessor();
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/* go multiprocessor mode */
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Cpu::start_secondary_processors(&_start_secondary_processors);
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}
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/**
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* Setup kernel enviroment after activating secondary processors
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*/
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extern "C" void init_kernel_multiprocessor()
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{
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/***********************************************************************
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** As updates on a cached kernel lock might not be visible to **
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** processors that have not enabled caches, we can't synchronize the **
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** activation of MMU and caches. Hence we must avoid write access to **
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** kernel data by now. **
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***********************************************************************/
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/* synchronize data view of all processors */
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Cpu::flush_data_caches();
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Cpu::invalidate_instruction_caches();
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Cpu::invalidate_control_flow_predictions();
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Cpu::data_synchronization_barrier();
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/* initialize processor in physical mode */
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Cpu::init_phys_kernel();
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/* switch to core address space */
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Cpu::init_virt_kernel(core_tlb_base, core_pd_id);
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/************************************
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** Now it's safe to use 'cmpxchg' **
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************************************/
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Lock::Guard guard(data_lock());
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/*******************************************
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** Now it's save to write to kernel data **
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*******************************************/
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/*
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* TrustZone initialization code
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*
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* FIXME This is a plattform specific feature
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*/
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init_trustzone(pic());
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/*
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* Enable performance counter
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*
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* FIXME This is an optional processor specific feature
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*/
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perf_counter()->enable();
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/* initialize interrupt controller */
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pic()->init_processor_local();
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unsigned const processor_id = Cpu::id();
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pic()->unmask(Timer::interrupt_id(processor_id), processor_id);
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/* as primary processor create the core main thread */
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if (Cpu::primary_id() == processor_id)
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{
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/* get stack memory that fullfills the constraints for core stacks */
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enum {
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STACK_ALIGNM = 1 << Genode::CORE_STACK_ALIGNM_LOG2,
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STACK_SIZE = DEFAULT_STACK_SIZE,
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};
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if (STACK_SIZE > STACK_ALIGNM - sizeof(Core_thread_id)) {
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PERR("stack size does not fit stack alignment of core");
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}
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static char s[STACK_SIZE] __attribute__((aligned(STACK_ALIGNM)));
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/* provide thread ident at the aligned base of the stack */
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*(Core_thread_id *)s = 0;
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/* start thread with stack pointer at the top of stack */
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static Native_utcb utcb;
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static Thread t(Priority::MAX, "core");
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_main_thread_id = t.id();
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_main_thread_utcb = &utcb;
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_main_thread_utcb->start_info()->init(t.id(), Genode::Native_capability());
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t.ip = (addr_t)CORE_MAIN;;
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t.sp = (addr_t)s + STACK_SIZE;
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t.init(multiprocessor()->select(processor_id), core_id(), &utcb, 1);
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/* kernel initialization finished */
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init_platform();
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}
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reset_lap_time(processor_id);
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}
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/**
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* Main routine of every kernel pass
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*/
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extern "C" void kernel()
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{
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data_lock().lock();
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unsigned const processor_id = Cpu::id();
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Processor * const processor = multiprocessor()->select(processor_id);
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Processor_scheduler * const scheduler = processor->scheduler();
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scheduler->head()->handle_exception(processor_id);
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scheduler->head()->proceed(processor_id);
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}
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Kernel::Mode_transition_control * Kernel::mtc()
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{
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/* create singleton processor context for kernel */
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Cpu_context * const cpu_context = unmanaged_singleton<Cpu_context>();
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/* initialize mode transition page */
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return unmanaged_singleton<Mode_transition_control>(cpu_context);
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}
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Kernel::Execution_context::~Execution_context() { }
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Kernel::Cpu_context::Cpu_context()
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{
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_init(STACK_SIZE);
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sp = (addr_t)kernel_stack;
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ip = (addr_t)kernel;
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core()->admit(this);
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}
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