88 lines
1.9 KiB
C++
88 lines
1.9 KiB
C++
/*
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* \brief CPU driver for core
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CPU_H_
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#define _CPU_H_
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/* core includes */
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#include <spec/arm_v7/cpu_support.h>
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namespace Genode
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{
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/**
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* Part of CPU state that is not switched on every mode transition
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*/
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class Cpu_lazy_state { };
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/**
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* CPU driver for core
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*/
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class Cpu;
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}
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namespace Kernel { using Genode::Cpu_lazy_state; }
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class Genode::Cpu : public Arm_v7
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{
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public:
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/**
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* Ensure that TLB insertions get applied
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*/
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static void tlb_insertions() { flush_tlb(); }
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/**
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* Return wether to retry an undefined user instruction after this call
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*/
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bool retry_undefined_instr(Cpu_lazy_state *) { return false; }
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/**
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* Post processing after a translation was added to a translation table
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*
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* \param addr virtual address of the translation
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* \param size size of the translation
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*/
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static void translation_added(addr_t const addr, size_t const size)
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{
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/*
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* The Cortex-A8 CPU can't use the L1 cache on page-table
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* walks. Therefore, as the page-tables lie in write-back cacheable
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* memory we've to clean the corresponding cache-lines even when a
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* page table entry is added. We only do this as core as the kernel
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* adds translations solely before MMU and caches are enabled.
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*/
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if (is_user()) Kernel::update_data_region(addr, size);
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else flush_data_caches();
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}
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id();
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/**
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* Return kernel name of the primary CPU
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*/
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static unsigned primary_id();
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/*************
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** Dummies **
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*************/
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static void prepare_proceeding(Cpu_lazy_state *, Cpu_lazy_state *) { }
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};
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void Genode::Arm_v7::finish_init_phys_kernel() { }
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#endif /* _CPU_H_ */
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