226 lines
6.2 KiB
C++
226 lines
6.2 KiB
C++
/*
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* \brief PL11x frame-buffer driver
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* \author Norman Feske
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* \author Stefan Kalkowski
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* \date 2010-02-17
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*/
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/*
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* Copyright (C) 2010-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* Genode includes */
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#include <base/printf.h>
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#include <base/sleep.h>
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#include <base/rpc_server.h>
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#include <io_mem_session/connection.h>
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#include <cap_session/connection.h>
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#include <dataspace/client.h>
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#include <timer_session/connection.h>
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#include <framebuffer_session/framebuffer_session.h>
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#include <root/component.h>
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#include <os/ring_buffer.h>
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/* device configuration */
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#include <pl11x_defs.h>
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#include <sp810_defs.h>
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#include <video_memory.h>
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/***********************************************
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** Implementation of the framebuffer service **
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***********************************************/
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namespace Framebuffer
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{
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enum {
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SCR_WIDTH = 640,
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SCR_HEIGHT = 480,
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LEFT_MARGIN = 64,
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RIGHT_MARGIN = 32,
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UPPER_MARGIN = 9,
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LOWER_MARGIN = 11,
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HSYNC_LEN = 64,
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VSYNC_LEN = 25,
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BYTES_PER_PIXEL = 2,
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FRAMEBUFFER_SIZE = SCR_WIDTH*SCR_HEIGHT*BYTES_PER_PIXEL,
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};
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class Session_component : public Genode::Rpc_object<Session>
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{
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private:
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Genode::Dataspace_capability _fb_ds_cap;
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Genode::Dataspace_client _fb_ds;
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Genode::addr_t _regs_base;
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Genode::addr_t _sys_regs_base;
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Timer::Connection _timer;
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enum {
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/**
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* Bit definitions of the lcd control register
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*/
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CTRL_ENABLED = 1 << 0,
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CTRL_BPP16 = 4 << 1,
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CTRL_BPP16_565 = 6 << 1,
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CTRL_TFT = 1 << 5,
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CTRL_BGR = 1 << 8,
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CTRL_POWER = 1 << 11,
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CTRL_VCOMP = 1 << 12,
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/**
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* Bit definitions for CLCDC timing.
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*/
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CLCDC_IVS = 1 << 11,
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CLCDC_IHS = 1 << 12,
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CLCDC_BCD = 1 << 26,
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};
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void sys_reg_write(unsigned reg, long value) {
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*(volatile long *)(_sys_regs_base + sizeof(long)*reg) = value; }
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long sys_reg_read(unsigned reg) {
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return *(volatile long *)(_sys_regs_base + sizeof(long)*reg); }
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void reg_write(unsigned reg, long value) {
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*(volatile long *)(_regs_base + sizeof(long)*reg) = value; }
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long reg_read(unsigned reg) {
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return *(volatile long *)(_regs_base + sizeof(long)*reg); }
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public:
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/**
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* Constructor
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*/
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Session_component(void *regs_base, void *sys_regs_base,
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Genode::Dataspace_capability fb_ds_cap)
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: _fb_ds_cap(fb_ds_cap), _fb_ds(_fb_ds_cap),
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_regs_base((Genode::addr_t)regs_base),
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_sys_regs_base((Genode::addr_t)sys_regs_base)
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{
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using namespace Genode;
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uint32_t tim0 = (SCR_WIDTH/16 - 1) << 2
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| (HSYNC_LEN - 1) << 8
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| (RIGHT_MARGIN - 1) << 16
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| (LEFT_MARGIN - 1) << 24;
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uint32_t tim1 = (SCR_HEIGHT - 1)
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| (VSYNC_LEN - 1) << 10
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| LOWER_MARGIN << 16
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| UPPER_MARGIN << 24;
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uint32_t tim2 = ((SCR_WIDTH - 1) << 16)
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| CLCDC_IVS | CLCDC_IHS | CLCDC_BCD;
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uint32_t tim3 = 0;
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uint32_t ctrl = reg_read(PL11X_REG_CTRL);
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/* reset video if already enabled */
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if (ctrl & CTRL_POWER) {
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ctrl &= ~CTRL_POWER;
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reg_write(PL11X_REG_CTRL, ctrl);
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_timer.msleep(100);
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}
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if (ctrl & CTRL_ENABLED) {
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ctrl &= ~CTRL_ENABLED;
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reg_write(PL11X_REG_CTRL, ctrl);
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_timer.msleep(100);
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}
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ctrl = CTRL_BGR | CTRL_ENABLED | CTRL_TFT | CTRL_VCOMP | CTRL_BPP16_565;
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/* init color-lcd oscillator */
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sys_reg_write(SP810_REG_LOCK, 0xa05f);
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sys_reg_write(SP810_REG_OSCCLCD, 0x2c77);
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sys_reg_write(SP810_REG_LOCK, 0);
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/* init video timing */
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reg_write(PL11X_REG_TIMING0, tim0);
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reg_write(PL11X_REG_TIMING1, tim1);
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reg_write(PL11X_REG_TIMING2, tim2);
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reg_write(PL11X_REG_TIMING3, tim3);
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/* set framebuffer address and ctrl register */
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reg_write(PL11X_REG_UPBASE, _fb_ds.phys_addr());
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reg_write(PL11X_REG_LPBASE, 0);
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reg_write(PL11X_REG_IMSC, 0);
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reg_write(PL11X_REG_CTRL, ctrl);
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_timer.msleep(100);
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/* power on */
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reg_write(PL11X_REG_CTRL, ctrl | CTRL_POWER);
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}
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Genode::Dataspace_capability dataspace() { return _fb_ds_cap; }
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Mode mode() const { return Mode(SCR_WIDTH, SCR_HEIGHT, Mode::RGB565); }
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void mode_sigh(Genode::Signal_context_capability) { }
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void refresh(int x, int y, int w, int h) { }
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};
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class Root : public Genode::Root_component<Session_component>
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{
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private:
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void *_lcd_regs_base;
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void *_sys_regs_base;
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Genode::Dataspace_capability _fb_ds_cap;
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protected:
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Session_component *_create_session(const char *args) {
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return new (md_alloc()) Session_component(_lcd_regs_base,
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_sys_regs_base,
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_fb_ds_cap); }
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public:
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Root(Genode::Rpc_entrypoint *session_ep, Genode::Allocator *md_alloc,
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void *lcd_regs_base, void *sys_regs_base,
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Genode::Dataspace_capability fb_ds_cap)
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: Genode::Root_component<Session_component>(session_ep, md_alloc),
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_lcd_regs_base(lcd_regs_base), _sys_regs_base(sys_regs_base),
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_fb_ds_cap(fb_ds_cap) { }
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};
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}
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using namespace Genode;
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int main(int, char **)
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{
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printf("--- pl11x framebuffer driver ---\n");
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/* locally map LCD control registers */
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Io_mem_connection lcd_io_mem(PL11X_LCD_PHYS, PL11X_LCD_SIZE);
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void *lcd_base = env()->rm_session()->attach(lcd_io_mem.dataspace());
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/* locally map system control registers */
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Io_mem_connection sys_mem(SP810_PHYS, SP810_SIZE);
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void *sys_base = env()->rm_session()->attach(sys_mem.dataspace());
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enum { STACK_SIZE = 4096 };
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static Cap_connection cap;
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static Rpc_entrypoint ep(&cap, STACK_SIZE, "fb_ep");
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Dataspace_capability fb_ds_cap =
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Framebuffer::alloc_video_memory(Framebuffer::FRAMEBUFFER_SIZE);
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/*
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* Let the entry point serve the framebuffer and input root interfaces
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*/
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static Framebuffer::Root fb_root(&ep, env()->heap(), lcd_base, sys_base, fb_ds_cap);
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env()->parent()->announce(ep.manage(&fb_root));
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sleep_forever();
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return 0;
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}
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