121 lines
3.0 KiB
C++
121 lines
3.0 KiB
C++
/*
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* \brief Secured Digital Host Controller
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* \author Martin Stein
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* \date 2016-12-13
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*/
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/*
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* Copyright (C) 2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* local includes */
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#include <sdhc.h>
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using namespace Sd_card;
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using namespace Genode;
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void Sdhc::_stop_transmission_finish_xfertyp(Xfertyp::access_t &xfertyp)
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{
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Xfertyp::Msbsel::set(xfertyp, 1);
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Xfertyp::Bcen::set(xfertyp, 1);
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Xfertyp::Dmaen::set(xfertyp, 1);
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}
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int Sdhc::_wait_for_cmd_complete_mb_finish(bool const reading)
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{
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if (reading) { return 0; }
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/*
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* The "Auto Command 12" feature of the ESDHC seems to be
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* broken for multi-block writes as it causes command-
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* timeout errors sometimes. Thus, we stop such transfers
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* manually.
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*/
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if (_stop_transmission()) { return -1; }
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/*
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* The manual termination of multi-block writes seems to leave
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* the card in a busy state sometimes. This causes
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* errors on subsequent commands. Thus, we have to synchronize
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* manually with the card-internal state.
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*/
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return _wait_for_card_ready_mbw() ? -1 : 0;
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}
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bool Sdhc::_issue_cmd_finish_xfertyp(Xfertyp::access_t &xfertyp,
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bool const transfer,
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bool const multiblock,
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bool const reading)
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{
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if (transfer) {
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Xfertyp::Bcen::set(xfertyp, 1);
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Xfertyp::Msbsel::set(xfertyp, 1);
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if (multiblock) {
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/*
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* The "Auto Command 12" feature of the ESDHC seems to be
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* broken for multi-block writes as it causes command-
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* timeout errors sometimes.
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*/
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if (reading) {
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Xfertyp::Ac12en::set(xfertyp, 1); }
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if (_use_dma) {
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Xfertyp::Dmaen::set(xfertyp, 1); }
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}
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Xfertyp::Dtdsel::set(xfertyp,
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reading ? Xfertyp::Dtdsel::READ : Xfertyp::Dtdsel::WRITE);
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}
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return _wait_for_cmd_allowed() ? false : true;
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}
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bool Sdhc::_supported_host_version(Hostver::access_t hostver)
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{
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return Hostver::Vvn::get(hostver) == 18 &&
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Hostver::Svn::get(hostver) == 1;
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}
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void Sdhc::_watermark_level(Wml::access_t &wml)
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{
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Wml::Wr_wml::set(wml, 16);
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Wml::Wr_brst_len::set(wml, 8);
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}
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void Sdhc::_reset_amendments()
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{
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/*
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* The SDHC specification says that a software reset shouldn't
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* have an effect on the the card detection circuit. The ESDHC
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* clears Sysctl::Ipgen, Sysctl::Hcken, and Sysctl::Peren
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* nonetheless which disables clocks that card detection relies
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* on.
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*/
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Sysctl::access_t sysctl = read<Sysctl>();
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Sysctl::Ipgen::set(sysctl, 1);
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Sysctl::Hcken::set(sysctl, 1);
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Sysctl::Peren::set(sysctl, 1);
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write<Sysctl>(sysctl);
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}
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void Sdhc::_clock_finish(Clock clock)
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{
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write<Sysctl::Dtocv>(Sysctl::Dtocv::SDCLK_TIMES_2_POW_27);
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switch (clock) {
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case CLOCK_INITIAL: _enable_clock(CLOCK_DIV_512); break;
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case CLOCK_OPERATIONAL: _enable_clock(CLOCK_DIV_8); break; }
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write<Sysctl::Dtocv>(Sysctl::Dtocv::SDCLK_TIMES_2_POW_27);
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}
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void Sdhc::_disable_clock_preparation() { }
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void Sdhc::_enable_clock_finish() { }
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