75 lines
1.8 KiB
C++
75 lines
1.8 KiB
C++
/*
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* \brief Programmable interrupt controller for core
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* \author Stefan Kalkowski
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* \date 2012-10-11
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _PIC__VEA9X4_TRUSTZONE_H_
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#define _PIC__VEA9X4_TRUSTZONE_H_
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/* core includes */
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#include <pic/arm_gic.h>
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#include <cpu.h>
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namespace Vea9x4_trustzone
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{
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using namespace Genode;
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/**
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* Programmable interrupt controller for core
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*/
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class Pic : public Arm_gic::Pic
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{
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public:
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/**
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* Constructor
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*/
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Pic() : Arm_gic::Pic(Genode::Cpu::PL390_DISTRIBUTOR_MMIO_BASE,
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Genode::Cpu::PL390_CPU_MMIO_BASE)
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{
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/* configure every shared peripheral interrupt */
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for (unsigned i=MIN_SPI; i <= _max_interrupt; i++) {
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_distr.write<Distr::Icfgr::Edge_triggered>(0, i);
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_distr.write<Distr::Ipriorityr::Priority>(0, i);
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_distr.write<Distr::Itargetsr::Cpu_targets>(
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Distr::Itargetsr::ALL, i);
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}
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/* disable the priority filter */
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_cpu.write<Cpu::Pmr::Priority>(0xff);
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/* signal secure IRQ via FIQ interface */
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_cpu.write<Cpu::Ctlr>(Cpu::Ctlr::Enable_grp0::bits(1) |
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Cpu::Ctlr::Enable_grp1::bits(1) |
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Cpu::Ctlr::Fiq_en::bits(1));
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/* use whole band of prios */
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_cpu.write<Cpu::Bpr::Binary_point>(Cpu::Bpr::NO_PREEMPTION);
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/* enable device */
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_distr.write<Distr::Ctlr>(Distr::Ctlr::Enable::bits(1));
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}
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/**
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* Mark interrupt 'i' unsecure
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*/
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void unsecure(unsigned const i) {
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_distr.write<Distr::Igroupr::Group_status>(1, i); }
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};
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}
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bool Arm_gic::Pic::_use_security_ext() { return 1; }
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#endif /* _PIC__VEA9X4_TRUSTZONE_H_ */
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