4d3fa001e0
On the Versatile Express Cortex A9x4 platform the first memory region 0x0 - 0x4000000 is a hardware remapped memory area, containing flash and DDR RAM copies and thus should not be added in addition to all DDR RAM regions and the SRAM region.
62 lines
1.4 KiB
C++
62 lines
1.4 KiB
C++
/*
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* \brief Platform implementations specific for base-hw and VEA9X4
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* \author Martin Stein
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* \date 2012-04-27
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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/* core includes */
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#include <platform.h>
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#include <board.h>
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#include <cpu.h>
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#include <pic.h>
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using namespace Genode;
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Native_region * Platform::_ram_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::RAM_0_BASE, Board::RAM_0_SIZE },
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{ Board::RAM_1_BASE, Board::RAM_1_SIZE },
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{ Board::RAM_2_BASE, Board::RAM_2_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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{ Board::MMIO_0_BASE, Board::MMIO_0_SIZE },
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{ Board::MMIO_1_BASE, Board::MMIO_1_SIZE },
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Native_region * Platform::_core_only_mmio_regions(unsigned const i)
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{
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static Native_region _regions[] =
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{
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/* Core timer and PIC */
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{ Board::CORTEX_A9_PRIVATE_MEM_BASE,
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Board::CORTEX_A9_PRIVATE_MEM_SIZE },
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/* Core UART */
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{ Board::PL011_0_MMIO_BASE, Board::PL011_0_MMIO_SIZE }
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};
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return i < sizeof(_regions)/sizeof(_regions[0]) ? &_regions[i] : 0;
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}
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Cpu::User_context::User_context() { cpsr = Psr::init_user(); }
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