170 lines
3.2 KiB
ArmAsm
170 lines
3.2 KiB
ArmAsm
/*
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* \brief Transition between kernel/userland
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* \author Adrian-Ken Rueegsegger
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* \author Martin Stein
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* \author Reto Buerki
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* \author Stefan Kalkowski
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* \date 2011-11-15
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.include "hw/spec/x86_64/gdt.s"
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/* offsets of member variables in a CPU context */
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.set IP_OFFSET, 17 * 8
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.set SP_OFFSET, 20 * 8
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/* tss segment constants */
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.set TSS_LIMIT, 0x68
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.set TSS_TYPE, 0x8900
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/* virtual addresses */
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.set BASE, 0xffffffc000000000
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.set TSS, BASE + (__tss - _begin)
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.set ISR, BASE
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.set ISR_ENTRY_SIZE, 12
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.set IDT_FLAGS_PRIVILEGED, 0x8e01
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.set IDT_FLAGS_UNPRIVILEGED, 0xee01
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.macro _isr_entry
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.align 4, 0x90
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.endm
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.macro _exception vector
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_isr_entry
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push $0
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push $\vector
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jmp _kernel_entry
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.endm
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.macro _exception_with_code vector
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_isr_entry
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nop
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nop
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push $\vector
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jmp _kernel_entry
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.endm
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.macro _idt_entry addr flags
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.word \addr & 0xffff
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.word 0x0008
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.word \flags
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.word (\addr >> 16) & 0xffff
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.long \addr >> 32
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.long 0
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.endm
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.macro _load_address label reg
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mov \label@GOTPCREL(%rip), %\reg
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.endm
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.section ".text.crt0"
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_begin:
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/*
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* On user exceptions the CPU has to jump to one of the following
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* Interrupt Service Routines (ISRs) to switch to a kernel context.
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*/
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_exception 0
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_exception 1
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_exception 2
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_exception 3
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_exception 4
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_exception 5
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_exception 6
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_exception 7
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_exception_with_code 8
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_exception 9
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_exception_with_code 10
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_exception_with_code 11
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_exception_with_code 12
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_exception_with_code 13
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_exception_with_code 14
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_exception 15
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_exception 16
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_exception_with_code 17
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_exception 18
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_exception 19
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.set vec, 20
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.rept 236
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_exception vec
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.set vec, vec + 1
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.endr
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_kernel_entry:
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pushq %rbp
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pushq %rsi
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pushq %rdi
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pushq %rdx
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pushq %rcx
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pushq %rbx
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pushq %rax
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %r9
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pushq %r8
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/* Restore kernel stack and continue kernel execution */
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_load_address kernel_stack rax
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_load_address kernel_stack_size rbx
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_load_address kernel rcx
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add (%rbx), %rax
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mov %rax, %rsp
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jmp *%rcx
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/*****************************************
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** Interrupt Descriptor Table (IDT) **
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** See Intel SDM Vol. 3A, section 6.10 **
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*****************************************/
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.global __idt
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.align 8
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__idt:
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/* first 128 entries */
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.set isr_addr, ISR
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.rept 0x80
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_idt_entry isr_addr IDT_FLAGS_PRIVILEGED
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.set isr_addr, isr_addr + ISR_ENTRY_SIZE
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.endr
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/* syscall entry 0x80 */
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_idt_entry isr_addr IDT_FLAGS_UNPRIVILEGED
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.set isr_addr, isr_addr + ISR_ENTRY_SIZE
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/* remaing entries */
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.rept 127
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_idt_entry isr_addr IDT_FLAGS_PRIVILEGED
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.set isr_addr, isr_addr + ISR_ENTRY_SIZE
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.endr
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/****************************************
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** Task State Segment (TSS) **
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** See Intel SDM Vol. 3A, section 7.7 **
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****************************************/
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.global __tss
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.align 8
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__tss:
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.space 36
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.global __tss_client_context_ptr
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__tss_client_context_ptr:
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.space 64
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_define_gdt TSS
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