296 lines
7.4 KiB
C++
296 lines
7.4 KiB
C++
/*
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* \brief x86_64 CPU driver for core
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* \author Adrian-Ken Rueegsegger
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* \author Martin stein
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* \author Reto Buerki
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* \author Stefan Kalkowski
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* \date 2015-02-06
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _CORE__SPEC__X86_64__CPU_H_
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#define _CORE__SPEC__X86_64__CPU_H_
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/* Genode includes */
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#include <util/register.h>
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#include <kernel/interface_support.h>
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#include <cpu/cpu_state.h>
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/* base includes */
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#include <base/internal/align_at.h>
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#include <base/internal/unmanaged_singleton.h>
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/* core includes */
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#include <fpu.h>
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namespace Genode {
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class Cpu;
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using sizet_arithm_t = __uint128_t;
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}
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class Genode::Cpu
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{
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public:
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struct Pd {};
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struct Pseudo_descriptor;
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struct Cr0; /* Control register 0 */
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struct Cr2; /* Control register 2 */
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struct Cr3; /* Control register 3 */
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struct Cr4; /* Control register 4 */
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/**
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* Task State Segment (TSS)
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*
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* See Intel SDM Vol. 3A, section 7.7
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*/
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struct Tss { static void init(); };
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/**
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* Interrupt Descriptor Table (IDT)
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*
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* See Intel SDM Vol. 3A, section 6.10
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*/
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struct Idt { static void init(); };
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/**
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* Global Descriptor Table (GDT)
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* See Intel SDM Vol. 3A, section 3.5.1
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*/
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struct Gdt { static void init(); };
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/**
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* Extend basic CPU state by members relevant for 'base-hw' only
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*/
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struct alignas(16) Context : Cpu_state
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{
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/**
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* Address of top-level paging structure.
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*/
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addr_t cr3;
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/**
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* Return base of assigned translation table
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*/
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addr_t translation_table() const { return cr3; }
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/**
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* Initialize context
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*
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* \param table physical base of appropriate translation table
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* \param core whether it is a core thread or not
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*/
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void init(addr_t const table, bool core);
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};
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/**
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* An usermode execution state
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*/
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struct User_context
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{
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Align_at<Context, 16> regs;
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Fpu::Context fpu_regs;
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/**
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* Support for kernel calls
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*/
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void user_arg_0(Kernel::Call_arg const arg) { regs->rdi = arg; }
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void user_arg_1(Kernel::Call_arg const arg) { regs->rsi = arg; }
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void user_arg_2(Kernel::Call_arg const arg) { regs->rdx = arg; }
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void user_arg_3(Kernel::Call_arg const arg) { regs->rcx = arg; }
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void user_arg_4(Kernel::Call_arg const arg) { regs->r8 = arg; }
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Kernel::Call_arg user_arg_0() const { return regs->rdi; }
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Kernel::Call_arg user_arg_1() const { return regs->rsi; }
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Kernel::Call_arg user_arg_2() const { return regs->rdx; }
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Kernel::Call_arg user_arg_3() const { return regs->rcx; }
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Kernel::Call_arg user_arg_4() const { return regs->r8; }
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};
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protected:
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Fpu _fpu;
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public:
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Fpu & fpu() { return _fpu; }
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/**
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* Wait for the next interrupt as cheap as possible
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*/
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static void wait_for_interrupt() { asm volatile ("pause"); }
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/**
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* Return wether to retry an undefined user instruction after this call
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*/
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bool retry_undefined_instr(Context&) { return false; }
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/**
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* Return kernel name of the executing CPU
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*/
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static unsigned executing_id() { return 0; }
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/**
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* Return kernel name of the primary CPU
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*/
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static unsigned primary_id() { return 0; }
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/**
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* Switch to new context
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*
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* \param context next CPU context
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*/
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inline void switch_to(User_context &context);
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};
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/**
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* Pseudo Descriptor
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*
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* See Intel SDM Vol. 3A, section 3.5.1
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*/
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struct Genode::Cpu::Pseudo_descriptor
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{
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uint16_t const limit = 0;
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uint64_t const base = 0;
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constexpr Pseudo_descriptor(uint16_t l, uint64_t b) : limit(l), base(b) {}
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} __attribute__((packed));
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struct Genode::Cpu::Cr0 : Register<64>
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{
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struct Pe : Bitfield< 0, 1> { }; /* Protection Enable */
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struct Mp : Bitfield< 1, 1> { }; /* Monitor Coprocessor */
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struct Em : Bitfield< 2, 1> { }; /* Emulation */
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struct Ts : Bitfield< 3, 1> { }; /* Task Switched */
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struct Et : Bitfield< 4, 1> { }; /* Extension Type */
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struct Ne : Bitfield< 5, 1> { }; /* Numeric Error */
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struct Wp : Bitfield<16, 1> { }; /* Write Protect */
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struct Am : Bitfield<18, 1> { }; /* Alignment Mask */
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struct Nw : Bitfield<29, 1> { }; /* Not Write-through */
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struct Cd : Bitfield<30, 1> { }; /* Cache Disable */
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struct Pg : Bitfield<31, 1> { }; /* Paging */
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static void write(access_t const v) {
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asm volatile ("mov %0, %%cr0" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mov %%cr0, %0" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Control register 2: Page-fault linear address
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*
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* See Intel SDM Vol. 3A, section 2.5.
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*/
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struct Genode::Cpu::Cr2 : Register<64>
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{
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struct Addr : Bitfield<0, 63> { };
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static access_t read()
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{
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access_t v;
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asm volatile ("mov %%cr2, %0" : "=r" (v) :: );
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return v;
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}
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};
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/**
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* Control register 3: Page-Directory base register
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*
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* See Intel SDM Vol. 3A, section 2.5.
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*/
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struct Genode::Cpu::Cr3 : Register<64>
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{
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struct Pwt : Bitfield<3,1> { }; /* Page-level write-through */
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struct Pcd : Bitfield<4,1> { }; /* Page-level cache disable */
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struct Pdb : Bitfield<12, 36> { }; /* Page-directory base address */
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static void write(access_t const v) {
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asm volatile ("mov %0, %%cr3" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mov %%cr3, %0" : "=r" (v) :: );
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return v;
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}
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/**
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* Return initialized value
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*
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* \param table base of targeted translation table
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*/
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static access_t init(addr_t const table) {
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return Pdb::masked(table); }
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};
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struct Genode::Cpu::Cr4 : Register<64>
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{
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struct Vme : Bitfield< 0, 1> { }; /* Virtual-8086 Mode Extensions */
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struct Pvi : Bitfield< 1, 1> { }; /* Protected-Mode Virtual IRQs */
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struct Tsd : Bitfield< 2, 1> { }; /* Time Stamp Disable */
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struct De : Bitfield< 3, 1> { }; /* Debugging Exceptions */
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struct Pse : Bitfield< 4, 1> { }; /* Page Size Extensions */
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struct Pae : Bitfield< 5, 1> { }; /* Physical Address Extension */
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struct Mce : Bitfield< 6, 1> { }; /* Machine-Check Enable */
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struct Pge : Bitfield< 7, 1> { }; /* Page Global Enable */
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struct Pce : Bitfield< 8, 1> { }; /* Performance-Monitoring Counter
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Enable*/
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struct Osfxsr : Bitfield< 9, 1> { }; /* OS Support for FXSAVE and
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FXRSTOR instructions*/
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struct Osxmmexcpt : Bitfield<10, 1> { }; /* OS Support for Unmasked
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SIMD/FPU Exceptions */
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struct Vmxe : Bitfield<13, 1> { }; /* VMX Enable */
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struct Smxe : Bitfield<14, 1> { }; /* SMX Enable */
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struct Fsgsbase : Bitfield<16, 1> { }; /* FSGSBASE-Enable */
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struct Pcide : Bitfield<17, 1> { }; /* PCIDE Enable */
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struct Osxsave : Bitfield<18, 1> { }; /* XSAVE and Processor Extended
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States-Enable */
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struct Smep : Bitfield<20, 1> { }; /* SMEP Enable */
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struct Smap : Bitfield<21, 1> { }; /* SMAP Enable */
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static void write(access_t const v) {
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asm volatile ("mov %0, %%cr4" :: "r" (v) : ); }
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static access_t read()
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{
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access_t v;
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asm volatile ("mov %%cr4, %0" : "=r" (v) :: );
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return v;
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}
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};
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void Genode::Cpu::switch_to(User_context &context)
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{
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_fpu.switch_to(context.fpu_regs);
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if ((context.regs->cs != 0x8) && (context.regs->cr3 != Cr3::read()))
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Cr3::write(context.regs->cr3);
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};
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#endif /* _CORE__SPEC__X86_64__CPU_H_ */
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