69 lines
1.7 KiB
C++
69 lines
1.7 KiB
C++
/*
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* \brief MMU initialization for Cortex A15
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* \author Stefan Kalkowski
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* \date 2017-04-09
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <spec/arm/cpu.h>
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void Bootstrap::Cpu::enable_mmu_and_caches(Genode::addr_t table)
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{
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/* invalidate TLB */
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Tlbiall::write(0);
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enum Memory_attributes {
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DEVICE_MEMORY = 0x04,
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NORMAL_MEMORY_UNCACHED = 0x44,
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NORMAL_MEMORY_CACHED = 0xff,
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};
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/* set memory attributes in indirection register */
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Mair0::access_t mair0 = 0;
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Mair0::Attr0::set(mair0, NORMAL_MEMORY_UNCACHED);
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Mair0::Attr1::set(mair0, DEVICE_MEMORY);
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Mair0::Attr2::set(mair0, NORMAL_MEMORY_CACHED);
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Mair0::Attr3::set(mair0, DEVICE_MEMORY);
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Mair0::write(mair0);
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/* do not use domains, but permission bits in table */
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Dacr::write(Dacr::D0::bits(1));
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Ttbr_64bit::access_t ttbr0 = Ttbr_64bit::Ba::masked(table);
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Ttbr_64bit::access_t ttbr1 = Ttbr_64bit::Ba::masked(table);
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Ttbr_64bit::Asid::set(ttbr0, 0);
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Ttbr0_64bit::write(ttbr0);
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Ttbr1_64bit::write(ttbr1);
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Ttbcr::access_t ttbcr = 0;
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Ttbcr::T0sz::set(ttbcr, 1);
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Ttbcr::T1sz::set(ttbcr, 0);
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Ttbcr::Irgn0::set(ttbcr, 1);
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Ttbcr::Irgn1::set(ttbcr, 1);
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Ttbcr::Orgn0::set(ttbcr, 1);
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Ttbcr::Orgn1::set(ttbcr, 1);
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Ttbcr::Sh0::set(ttbcr, 0b10);
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Ttbcr::Sh1::set(ttbcr, 0b10);
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Ttbcr::Eae::set(ttbcr, 1);
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Ttbcr::write(ttbcr);
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Sctlr::access_t sctlr = Sctlr::read();
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Sctlr::C::set(sctlr, 1);
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Sctlr::I::set(sctlr, 1);
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Sctlr::V::set(sctlr, 1);
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Sctlr::A::set(sctlr, 0);
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Sctlr::M::set(sctlr, 1);
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Sctlr::Z::set(sctlr, 1);
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Sctlr::write(sctlr);
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/* invalidate branch predictor */
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Bpiall::write(0);
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}
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