4d3d4ecca0
With this, we get rid of platform specific timer interfaces. The new Timer class does the same as the old Clock class and has a generic interface. The old Timer class was merely used by the old Clock class. Also, we get rid of having only one timer instance which we tell with each method call for which CPU it shall be done. Instead now each Cpu object has its own Timer member that knows the CPU it works for. Also, rename all "tics" to "ticks". Fixes #2347
104 lines
2.3 KiB
C++
104 lines
2.3 KiB
C++
/*
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* \brief Timer driver for core
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* \author Adrian-Ken Rueegsegger
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* \author Reto Buerki
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* \author Martin Stein
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* \date 2015-02-06
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*/
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/*
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* Copyright (C) 2015-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <hw/spec/x86_64/x86_64.h>
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/* core includes */
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#include <kernel/timer.h>
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#include <platform.h>
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using namespace Genode;
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using namespace Kernel;
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uint32_t Timer_driver::pit_calc_timer_freq(void)
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{
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uint32_t t_start, t_end;
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/* Set channel gate high and disable speaker */
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outb(PIT_CH2_GATE, (inb(0x61) & ~0x02) | 0x01);
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/* Set timer counter (mode 0, binary count) */
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outb(PIT_MODE, 0xb0);
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outb(PIT_CH2_DATA, PIT_SLEEP_TICS & 0xff);
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outb(PIT_CH2_DATA, PIT_SLEEP_TICS >> 8);
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write<Tmr_initial>(~0U);
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t_start = read<Tmr_current>();
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while ((inb(PIT_CH2_GATE) & 0x20) == 0)
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{
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asm volatile("pause" : : : "memory");
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}
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t_end = read<Tmr_current>();
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write<Tmr_initial>(0);
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return (t_start - t_end) / PIT_SLEEP_MS;
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}
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Timer_driver::Timer_driver(unsigned)
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: Mmio(Platform::mmio_to_virt(Hw::Cpu_memory_map::MMIO_LAPIC_BASE))
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{
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write<Divide_configuration::Divide_value>(
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Divide_configuration::Divide_value::MAX);
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/* Enable LAPIC timer in one-shot mode */
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write<Tmr_lvt::Vector>(Board::TIMER_VECTOR_KERNEL);
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write<Tmr_lvt::Delivery>(0);
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write<Tmr_lvt::Mask>(0);
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write<Tmr_lvt::Timer_mode>(0);
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/* Calculate timer frequency */
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ticks_per_ms = pit_calc_timer_freq();
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}
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void Timer::init_cpu_local()
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{
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/**
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* Disable PIT timer channel. This is necessary since BIOS sets up
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* channel 0 to fire periodically.
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*/
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outb(Driver::PIT_MODE, 0x30);
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outb(Driver::PIT_CH0_DATA, 0);
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outb(Driver::PIT_CH0_DATA, 0);
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}
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void Timer::_start_one_shot(time_t const ticks) {
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_driver.write<Driver::Tmr_initial>(ticks); }
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time_t Timer::_ticks_to_us(time_t const ticks) const {
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return (ticks / _driver.ticks_per_ms) * 1000; }
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time_t Timer::us_to_ticks(time_t const us) const {
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return (us / 1000) * _driver.ticks_per_ms; }
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time_t Timer::_max_value() const {
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return (Driver::Tmr_initial::access_t)~0; }
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time_t Timer::_value() {
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return _driver.read<Driver::Tmr_current>(); }
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unsigned Timer::interrupt_id() const {
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return Board::TIMER_VECTOR_KERNEL; }
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