4d3d4ecca0
With this, we get rid of platform specific timer interfaces. The new Timer class does the same as the old Clock class and has a generic interface. The old Timer class was merely used by the old Clock class. Also, we get rid of having only one timer instance which we tell with each method call for which CPU it shall be done. Instead now each Cpu object has its own Timer member that knows the CPU it works for. Also, rename all "tics" to "ticks". Fixes #2347
183 lines
3.1 KiB
C++
183 lines
3.1 KiB
C++
/*
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* \brief Timer driver for core
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* \author Martin stein
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* \date 2013-01-10
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Kernel OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _TIMER_DRIVER_H_
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#define _TIMER_DRIVER_H_
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/* Kernel includes */
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#include <util/mmio.h>
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/* base-hw includes */
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#include <kernel/types.h>
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namespace Kernel { class Timer_driver; }
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struct Kernel::Timer_driver : Genode::Mmio
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{
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enum {
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PRESCALER = 1,
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DIV_MUX = 0,
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};
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/**
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* MCT configuration
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*/
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struct Mct_cfg : Register<0x0, 32>
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{
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struct Prescaler : Bitfield<0, 8> { };
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struct Div_mux : Bitfield<8, 3> { };
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};
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/*******************
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** Local timer 0 **
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*******************/
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/**
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* Free running counter buffer
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*/
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struct L0_frcntb : Register<0x310, 32> { };
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/**
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* Configuration
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*/
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struct L0_tcon : Register<0x320, 32>
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{
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struct Frc_start : Bitfield<3, 1> { };
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};
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/**
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* Expired status
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*/
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struct L0_int_cstat : Register<0x330, 32, true>
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{
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struct Frcnt : Bitfield<1, 1> { };
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};
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/**
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* Interrupt enable
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*/
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struct L0_int_enb : Register<0x334, 32>
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{
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struct Frceie : Bitfield<1, 1> { };
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};
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/**
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* Write status
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*/
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struct L0_wstat : Register<0x340, 32, true>
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{
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struct Frcntb : Bitfield<2, 1> { };
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struct Tcon : Bitfield<3, 1> { };
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};
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struct L0_frcnto : Register<0x314, 32> { };
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/**
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* Start and stop counting
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*/
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void run_0(bool const run)
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{
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acked_write<L0_tcon, L0_wstat::Tcon>
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(L0_tcon::Frc_start::bits(run));
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}
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/*******************
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** Local timer 1 **
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*******************/
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/**
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* Free running counter buffer
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*/
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struct L1_frcntb : Register<0x410, 32> { };
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/**
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* Configuration
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*/
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struct L1_tcon : Register<0x420, 32>
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{
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struct Frc_start : Bitfield<3, 1> { };
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};
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/**
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* Expired status
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*/
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struct L1_int_cstat : Register<0x430, 32, true>
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{
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struct Frcnt : Bitfield<1, 1> { };
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};
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/**
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* Interrupt enable
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*/
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struct L1_int_enb : Register<0x434, 32>
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{
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struct Frceie : Bitfield<1, 1> { };
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};
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/**
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* Write status
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*/
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struct L1_wstat : Register<0x440, 32, true>
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{
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struct Frcntb : Bitfield<2, 1> { };
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struct Tcon : Bitfield<3, 1> { };
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};
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struct L1_frcnto : Register<0x414, 32> { };
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/**
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* Start and stop counting
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*/
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void run_1(bool const run)
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{
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acked_write<L1_tcon, L1_wstat::Tcon>
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(L1_tcon::Frc_start::bits(run));
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}
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/********************
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** Helper methods **
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********************/
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/**
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* Write to reg that replies via ack bit and clear ack bit
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*/
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template <typename DEST, typename ACK>
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void acked_write(typename DEST::Register_base::access_t const v)
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{
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typedef typename DEST::Register_base Dest;
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typedef typename ACK::Bitfield_base Ack;
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write<Dest>(v);
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while (!read<Ack>());
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write<Ack>(1);
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}
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/**
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* Calculate amount of ticks per ms for specific input clock
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*
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* \param clock input clock
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*/
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time_t static calc_ticks_per_ms(unsigned const clock) {
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return clock / (PRESCALER + 1) / (1 << DIV_MUX) / 1000; }
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unsigned const ticks_per_ms;
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unsigned const cpu_id;
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Timer_driver(unsigned cpu_id);
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};
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#endif /* _TIMER_DRIVER_H_ */
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