genode/repos/base/include/spec/x86_64/cpu/cpu_state.h
Stefan Kalkowski 4e97a6511b hw: switch page-tables only when necessary
* Instead of always re-load page-tables when a thread context is switched
  only do this when another user PD's thread is the next target,
  core-threads are always executed within the last PD's page-table set
* remove the concept of the mode transition
* instead map the exception vector once in bootstrap code into kernel's
  memory segment
* when a new page directory is constructed for a user PD, copy over the
  top-level kernel segment entries on RISCV and X86, on ARM we use a designated
  page directory register for the kernel segment
* transfer the current CPU id from bootstrap to core/kernel in a register
  to ease first stack address calculation
* align cpu context member of threads and vms, because of x86 constraints
  regarding the stack-pointer loading
* introduce Align_at template for members with alignment constraints
* let the x86 hardware do part of the context saving in ISS, by passing
  the thread context into the TSS before leaving to user-land
* use one exception vector for all ARM platforms including Arm_v6

Fix #2091
2017-10-19 13:31:18 +02:00

63 lines
1.4 KiB
C++

/*
* \brief CPU state
* \author Adrian-Ken Rueegsegger
* \author Christian Prochaska
* \author Reto Buerki
* \author Stefan Kalkowski
* \date 2011-04-15
*
* This file contains the x86_64-specific part of the CPU state.
*/
/*
* Copyright (C) 2011-2017 Genode Labs GmbH
*
* This file is part of the Genode OS framework, which is distributed
* under the terms of the GNU Affero General Public License version 3.
*/
#ifndef _INCLUDE__SPEC__X86_64__CPU__CPU_STATE_H_
#define _INCLUDE__SPEC__X86_64__CPU__CPU_STATE_H_
#include <base/stdint.h>
namespace Genode { struct Cpu_state; }
struct Genode::Cpu_state
{
enum Cpu_exception {
UNDEFINED_INSTRUCTION = 0x06,
NO_MATH_COPROC = 0x07,
PAGE_FAULT = 0x0e,
SUPERVISOR_CALL = 0x80,
INTERRUPTS_START = 0x20,
RESET = 0xfe,
INTERRUPTS_END = 0xff,
};
addr_t r8 = 0;
addr_t r9 = 0;
addr_t r10 = 0;
addr_t r11 = 0;
addr_t r12 = 0;
addr_t r13 = 0;
addr_t r14 = 0;
addr_t r15 = 0;
addr_t rax = 0;
addr_t rbx = 0;
addr_t rcx = 0;
addr_t rdx = 0;
addr_t rdi = 0;
addr_t rsi = 0;
addr_t rbp = 0;
addr_t trapno = RESET;
addr_t errcode = 0;
addr_t ip = 0;
addr_t cs = 0;
addr_t eflags = 0;
addr_t sp = 0;
addr_t ss = 0;
};
#endif /* _INCLUDE__SPEC__X86_64__CPU__CPU_STATE_H_ */