4e97a6511b
* Instead of always re-load page-tables when a thread context is switched only do this when another user PD's thread is the next target, core-threads are always executed within the last PD's page-table set * remove the concept of the mode transition * instead map the exception vector once in bootstrap code into kernel's memory segment * when a new page directory is constructed for a user PD, copy over the top-level kernel segment entries on RISCV and X86, on ARM we use a designated page directory register for the kernel segment * transfer the current CPU id from bootstrap to core/kernel in a register to ease first stack address calculation * align cpu context member of threads and vms, because of x86 constraints regarding the stack-pointer loading * introduce Align_at template for members with alignment constraints * let the x86 hardware do part of the context saving in ISS, by passing the thread context into the TSS before leaving to user-land * use one exception vector for all ARM platforms including Arm_v6 Fix #2091
63 lines
1.4 KiB
C++
63 lines
1.4 KiB
C++
/*
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* \brief CPU state
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* \author Adrian-Ken Rueegsegger
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* \author Christian Prochaska
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* \author Reto Buerki
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* \author Stefan Kalkowski
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* \date 2011-04-15
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*
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* This file contains the x86_64-specific part of the CPU state.
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _INCLUDE__SPEC__X86_64__CPU__CPU_STATE_H_
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#define _INCLUDE__SPEC__X86_64__CPU__CPU_STATE_H_
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#include <base/stdint.h>
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namespace Genode { struct Cpu_state; }
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struct Genode::Cpu_state
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{
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enum Cpu_exception {
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UNDEFINED_INSTRUCTION = 0x06,
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NO_MATH_COPROC = 0x07,
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PAGE_FAULT = 0x0e,
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SUPERVISOR_CALL = 0x80,
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INTERRUPTS_START = 0x20,
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RESET = 0xfe,
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INTERRUPTS_END = 0xff,
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};
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addr_t r8 = 0;
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addr_t r9 = 0;
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addr_t r10 = 0;
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addr_t r11 = 0;
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addr_t r12 = 0;
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addr_t r13 = 0;
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addr_t r14 = 0;
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addr_t r15 = 0;
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addr_t rax = 0;
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addr_t rbx = 0;
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addr_t rcx = 0;
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addr_t rdx = 0;
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addr_t rdi = 0;
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addr_t rsi = 0;
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addr_t rbp = 0;
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addr_t trapno = RESET;
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addr_t errcode = 0;
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addr_t ip = 0;
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addr_t cs = 0;
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addr_t eflags = 0;
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addr_t sp = 0;
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addr_t ss = 0;
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};
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#endif /* _INCLUDE__SPEC__X86_64__CPU__CPU_STATE_H_ */
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