165 lines
3.7 KiB
C++
165 lines
3.7 KiB
C++
/*
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* \brief Regulator driver for power management unit of Exynos4412 SoC
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* \author Alexy Gallardo Segura <alexy@uclv.cu>
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* \author Humberto Lopez Leon <humberto@uclv.cu>
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* \author Reinier Millo Sanchez <rmillo@uclv.cu>
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* \date 2015-07-08
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _DRIVERS__PLATFORM__SPEC__ODROID_X2__PMU_H_
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#define _DRIVERS__PLATFORM__SPEC__ODROID_X2__PMU_H_
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#include <regulator/consts.h>
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#include <regulator/driver.h>
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#include <drivers/board_base.h>
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#include <os/attached_mmio.h>
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using namespace Regulator;
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class Pmu : public Regulator::Driver,
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public Genode::Attached_mmio
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{
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private:
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template <unsigned OFFSET>
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struct Control : Register <OFFSET, 32>
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{
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struct Enable : Register<OFFSET, 32>::template Bitfield<0, 1> { };
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};
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template <unsigned OFFSET>
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struct Configuration : Register <OFFSET, 32>
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{
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struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 3> { };
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};
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template <unsigned OFFSET>
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struct Status : Register <OFFSET, 32>
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{
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struct Stat : Register<OFFSET, 32>::template Bitfield<0, 3> { };
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};
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template <unsigned OFFSET>
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struct Sysclk_configuration : Register <OFFSET, 32>
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{
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struct Local_pwr_cfg : Register<OFFSET, 32>::template Bitfield<0, 1> { };
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};
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template <unsigned OFFSET>
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struct Sysclk_status : Register <OFFSET, 32>
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{
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struct Stat : Register<OFFSET, 32>::template Bitfield<0, 1> { };
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};
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struct Hdmi_phy_control : Register<0x700, 32>
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{
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struct Enable : Bitfield<0, 1> { };
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struct Div_ratio : Bitfield<16, 10> { };
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};
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typedef Control<0x0704> Usbdrd_phy_control;
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typedef Control<0x0708> Usbhost_phy1_control;
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typedef Control<0x70c> Usbhost_phy2_control;
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void _enable(unsigned long id)
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{
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switch (id) {
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case PWR_USB20:
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write<Usbdrd_phy_control::Enable>(1);
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write<Usbhost_phy1_control::Enable>(1);
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write<Usbhost_phy2_control::Enable>(1);
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break;
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case PWR_HDMI: {
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Hdmi_phy_control::access_t hpc = read<Hdmi_phy_control>();
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Hdmi_phy_control::Div_ratio::set(hpc, 150);
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Hdmi_phy_control::Enable::set(hpc, 1);
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write<Hdmi_phy_control>(hpc);
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break; }
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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}
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void _disable(unsigned long id)
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{
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switch (id) {
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case PWR_USB20:
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write<Usbdrd_phy_control::Enable>(0);
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write<Usbhost_phy1_control::Enable>(0);
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write<Usbhost_phy2_control::Enable>(0);
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break;
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case PWR_HDMI:
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write<Hdmi_phy_control::Enable>(0);
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break;
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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}
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public:
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/**
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* Constructor
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*/
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Pmu() : Genode::Attached_mmio(Genode::Board_base::PMU_MMIO_BASE,
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Genode::Board_base::PMU_MMIO_SIZE)
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{
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write<Usbdrd_phy_control::Enable>(0);
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write<Usbhost_phy1_control::Enable>(0);
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write<Usbhost_phy2_control::Enable>(0);
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write<Hdmi_phy_control::Enable>(0);
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}
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/********************************
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** Regulator driver interface **
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********************************/
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void level(Regulator_id id, unsigned long level)
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{
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switch (id) {
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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}
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unsigned long level(Regulator_id id)
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{
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switch (id) {
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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return 0;
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}
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void state(Regulator_id id, bool enable)
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{
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if (enable)
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_enable(id);
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else
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_disable(id);
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}
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bool state(Regulator_id id)
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{
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switch (id) {
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case PWR_USB20:
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return read<Usbdrd_phy_control::Enable>();
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default:
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PWRN("Unsupported for %s", names[id].name);
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}
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return true;
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}
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};
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#endif /* _DRIVERS__PLATFORM__SPEC__ODROID_X2__PMU_H_ */
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