304 lines
6.4 KiB
ArmAsm
304 lines
6.4 KiB
ArmAsm
/*
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* \brief Transition between kernel/userland
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* \author Adrian-Ken Rueegsegger
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* \author Martin Stein
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* \author Reto Buerki
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* \author Stefan Kalkowski
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* \date 2011-11-15
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*/
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/*
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* Copyright (C) 2011-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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.include "macros.s"
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/* size of pointer to CPU context */
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.set CONTEXT_PTR_SIZE, 1 * 8
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/* globally mapped buffer storage */
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.set BUFFER_SIZE, 6 * 8
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/* offsets of the member variables in a CPU context */
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.set SP_OFFSET, 1 * 8
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.set R8_OFFSET, 2 * 8
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.set RAX_OFFSET, 10 * 8
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.set ERRCODE_OFFSET, 17 * 8
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.set FLAGS_OFFSET, 18 * 8
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.set TRAPNO_OFFSET, 19 * 8
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.set CR3_OFFSET, 21 * 8
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/* tss segment constants */
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.set TSS_LIMIT, 0x68
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.set TSS_TYPE, 0x8900
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/* mtc virt addresses */
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.set MT_BASE, 0xffffffc000000000
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.set MT_TSS, MT_BASE + (_mt_tss - _mt_begin)
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.set MT_ISR, MT_BASE
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.set MT_IRQ_STACK, MT_BASE + (_mt_kernel_interrupt_stack - _mt_begin)
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.set MT_ISR_ENTRY_SIZE, 12
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.set IDT_FLAGS_PRIVILEGED, 0x8e00
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.set IDT_FLAGS_UNPRIVILEGED, 0xee00
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.macro _isr_entry
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.align 4, 0x90
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.endm
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.macro _exception vector
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_isr_entry
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push $0
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push $\vector
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jmp _mt_kernel_entry_pic
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.endm
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.macro _exception_with_code vector
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_isr_entry
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nop
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nop
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push $\vector
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jmp _mt_kernel_entry_pic
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.endm
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.macro _idt_entry addr flags
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.word \addr & 0xffff
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.word 0x0008
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.word \flags
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.word (\addr >> 16) & 0xffff
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.long \addr >> 32
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.long 0
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.endm
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.macro _load_address label reg
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mov \label@GOTPCREL(%rip), %\reg
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.endm
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.section ".text.crt0"
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/*
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* Page aligned base of mode transition code.
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*
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* This position independent code switches between a kernel context and a
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* user context and thereby between their address spaces. Due to the latter
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* it must be mapped executable to the same region in every address space.
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* To enable such switching, the kernel context must be stored within this
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* region, thus one should map it solely accessable for privileged modes.
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*/
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.p2align MIN_PAGE_SIZE_LOG2
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.global _mt_begin
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_mt_begin:
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/*
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* On user exceptions the CPU has to jump to one of the following
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* Interrupt Service Routines (ISRs) to switch to a kernel context.
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*/
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_exception 0
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_exception 1
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_exception 2
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_exception 3
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_exception 4
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_exception 5
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_exception 6
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_exception 7
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_exception_with_code 8
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_exception 9
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_exception_with_code 10
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_exception_with_code 11
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_exception_with_code 12
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_exception_with_code 13
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_exception_with_code 14
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_exception 15
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_exception 16
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_exception_with_code 17
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_exception 18
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_exception 19
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.set vec, 20
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.rept 236
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_exception vec
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.set vec, vec + 1
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.endr
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/* space for a copy of the kernel context */
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.p2align 2
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.global _mt_master_context_begin
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_mt_master_context_begin:
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/* space must be at least as large as 'Cpu_state' */
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.space 22*8
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.global _mt_master_context_end
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_mt_master_context_end:
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/* space for a client context-pointer per CPU */
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.p2align 2
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.global _mt_client_context_ptr
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_mt_client_context_ptr:
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.space CONTEXT_PTR_SIZE
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/* a globally mapped buffer per CPU */
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.p2align 2
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.global _mt_buffer
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_mt_buffer:
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.space BUFFER_SIZE
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.global _mt_kernel_entry_pic
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_mt_kernel_entry_pic:
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/* Copy client context RAX to buffer */
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pushq %rax
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/* Switch to kernel page tables */
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_load_address _mt_master_context_begin rax
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mov CR3_OFFSET(%rax), %rax
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mov %rax, %cr3
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/* Save information on interrupt stack frame in client context */
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_load_address _mt_client_context_ptr rax
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mov (%rax), %rax
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popq RAX_OFFSET(%rax)
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popq TRAPNO_OFFSET(%rax)
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popq ERRCODE_OFFSET(%rax)
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popq (%rax)
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popq FLAGS_OFFSET(%rax) /* Discard cs */
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popq FLAGS_OFFSET(%rax)
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popq SP_OFFSET(%rax)
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/* Save register values to client context */
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lea ERRCODE_OFFSET(%rax), %rsp
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pushq %rbp
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pushq %rsi
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pushq %rdi
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pushq %rdx
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pushq %rcx
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pushq %rbx
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sub $8, %rsp
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %r11
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pushq %r10
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pushq %r9
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pushq %r8
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/* Restore kernel stack and continue kernel execution */
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_load_address _mt_master_context_begin rsp
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mov (%rsp), %rax
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mov SP_OFFSET(%rsp), %rsp
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jmp *%rax
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.global _mt_user_entry_pic
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_mt_user_entry_pic:
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/* Prepare stack frame in mt buffer (Intel SDM Vol. 3A, figure 6-8) */
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_load_address _mt_client_context_ptr rax
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mov (%rax), %rax
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_load_address _mt_buffer rsp
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add $BUFFER_SIZE, %rsp
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pushq $0x23
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pushq SP_OFFSET(%rax)
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pushq FLAGS_OFFSET(%rax)
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pushq $0x1b
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pushq (%rax)
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/* Restore register values from client context */
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lea R8_OFFSET(%rax), %rsp
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_load_address _mt_buffer rbx
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popq %r8
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popq %r9
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popq %r10
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popq %r11
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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popq (%rbx)
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popq %rbx
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popq %rcx
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popq %rdx
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popq %rdi
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popq %rsi
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popq %rbp
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/* Switch page tables */
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mov CR3_OFFSET(%rax), %rax
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mov %rax, %cr3
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/* Set stack back to mt buffer and restore client RAX */
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_load_address _mt_buffer rsp
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popq %rax
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iretq
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/* VM entry: Switch to guest VM */
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.global _vt_vm_entry
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_vt_vm_entry:
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sti
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mov $1, %rax
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vmcall
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/*****************************************
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** Interrupt Descriptor Table (IDT) **
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** See Intel SDM Vol. 3A, section 6.10 **
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*****************************************/
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.global _mt_idt
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.align 8
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_mt_idt:
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/* first 128 entries */
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.set isr_addr, MT_ISR
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.rept 0x80
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_idt_entry isr_addr IDT_FLAGS_PRIVILEGED
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.set isr_addr, isr_addr + MT_ISR_ENTRY_SIZE
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.endr
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/* syscall entry 0x80 */
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_idt_entry isr_addr IDT_FLAGS_UNPRIVILEGED
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.set isr_addr, isr_addr + MT_ISR_ENTRY_SIZE
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/* remaing entries */
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.rept 127
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_idt_entry isr_addr IDT_FLAGS_PRIVILEGED
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.set isr_addr, isr_addr + MT_ISR_ENTRY_SIZE
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.endr
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/****************************************
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** Task State Segment (TSS) **
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** See Intel SDM Vol. 3A, section 7.7 **
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****************************************/
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.global _mt_tss
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.align 8
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_mt_tss:
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.space 4
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.quad MT_IRQ_STACK
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.quad MT_IRQ_STACK
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.quad MT_IRQ_STACK
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.space 76
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_define_gdt MT_TSS
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/************************************************
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** Temporary interrupt stack **
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** Set as RSP for privilege levels 0-2 in TSS **
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** See Intel SDM Vol. 3A, section 7.7 **
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************************************************/
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.p2align 8
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.space 7 * 8
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.global _mt_kernel_interrupt_stack
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_mt_kernel_interrupt_stack:
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/* end of the mode transition code */
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.global _mt_end
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_mt_end:
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1: jmp 1b
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