55 lines
1.5 KiB
C++
55 lines
1.5 KiB
C++
/*
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* \brief Specific i.MX53 bootstrap implementations
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* \author Stefan Kalkowski
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* \date 2012-10-24
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*/
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/*
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* Copyright (C) 2012-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#include <platform.h>
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#include <drivers/defs/imx53_trustzone.h>
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#include <spec/arm/imx_aipstz.h>
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#include <spec/arm/imx_csu.h>
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using namespace Board;
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bool Board::secure_irq(unsigned i)
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{
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if (i == EPIT_1_IRQ) return true;
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if (i == EPIT_2_IRQ) return true;
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if (i == SDHC_IRQ) return true;
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return false;
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}
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Bootstrap::Platform::Board::Board()
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: early_ram_regions(Memory_region { Trustzone::SECURE_RAM_BASE,
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Trustzone::SECURE_RAM_SIZE }),
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core_mmio(Memory_region { UART_1_MMIO_BASE, UART_1_MMIO_SIZE },
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Memory_region { EPIT_1_MMIO_BASE, EPIT_1_MMIO_SIZE },
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Memory_region { IRQ_CONTROLLER_BASE, IRQ_CONTROLLER_SIZE },
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Memory_region { CSU_BASE, CSU_SIZE })
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{
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Aipstz aipstz_1(AIPS_1_MMIO_BASE);
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Aipstz aipstz_2(AIPS_2_MMIO_BASE);
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Pic pic {};
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/* set monitor mode exception vector entry */
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Cpu::Mvbar::write(Hw::Mm::system_exception_vector().base);
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/* enable coprocessor 10 + 11 access for TZ VMs */
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Cpu::Nsacr::access_t v = 0;
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Cpu::Nsacr::Cpnsae10::set(v, 1);
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Cpu::Nsacr::Cpnsae11::set(v, 1);
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Cpu::Nsacr::write(v);
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/* configure central security unit */
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Csu csu(CSU_BASE, true, false, true, false);
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}
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