135 lines
2.9 KiB
C++
135 lines
2.9 KiB
C++
/*
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* \brief TLB driver for core
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* \author Martin Stein
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* \date 2012-02-22
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _TLB__ARM_V7_H_
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#define _TLB__ARM_V7_H_
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/* core includes */
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#include <tlb/arm.h>
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#include <processor_driver.h>
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namespace Arm_v7
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{
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/**
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* First level translation table
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*/
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class Section_table;
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}
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class Arm_v7::Section_table : public Arm::Section_table
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{
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private:
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typedef Arm::Section_table Base;
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typedef Genode::addr_t addr_t;
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typedef Genode::size_t size_t;
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public:
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/**
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* Link to second level translation-table
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*/
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struct Page_table_descriptor : Base::Page_table_descriptor
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{
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struct Ns : Bitfield<3, 1> { }; /* non-secure bit */
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/**
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* Compose descriptor value
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*/
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static access_t create(Arm::Page_table * const pt,
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Section_table * const st)
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{
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access_t const ns = Ns::bits(!st->secure());
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return Base::Page_table_descriptor::create(pt) | ns;
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}
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};
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/**
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* Section translation descriptor
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*/
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struct Section : Base::Section
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{
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struct Ns : Bitfield<19, 1> { }; /* non-secure bit */
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/**
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* Compose descriptor value
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*/
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static access_t create(Page_flags const & flags,
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addr_t const pa, Section_table * const st)
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{
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access_t const ns = Ns::bits(!st->secure());
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return Base::Section::create(flags, pa) | ns;
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}
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};
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protected:
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/* if this table is dedicated to secure mode or to non-secure mode */
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bool const _secure;
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public:
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/**
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* Constructor
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*/
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Section_table() : _secure(Processor_driver::secure_mode()) { }
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/**
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* Insert one atomic translation into this table
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*
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* For details see 'Base::insert_translation'
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*/
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size_t insert_translation(addr_t const vo, addr_t const pa,
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size_t const size_log2,
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Page_flags const & flags,
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void * const p = 0)
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{
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return Base::insert_translation(vo, pa, size_log2, flags, this, p);
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}
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/**
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* Insert translations for given area, do not permit displacement
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*
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* \param vo virtual offset within this table
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* \param s area size
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* \param io_mem wether the area maps MMIO
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*/
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void map_core_area(addr_t vo, size_t s, bool const io_mem)
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{
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Base::map_core_area(vo, s, io_mem, this);
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}
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/***************
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** Accessors **
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***************/
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bool secure() const { return _secure; }
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};
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template <typename T>
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static typename T::access_t
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Arm::memory_region_attr(Page_flags const & flags)
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{
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typedef typename T::Tex Tex;
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typedef typename T::C C;
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typedef typename T::B B;
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if (flags.device) { return Tex::bits(2); }
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if (flags.cacheable) { return Tex::bits(5) | B::bits(1); }
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return Tex::bits(6) | C::bits(1);
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}
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#endif /* _TLB__ARM_V7_H_ */
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