125 lines
2.6 KiB
C++
125 lines
2.6 KiB
C++
/*
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* \brief Interrupt controller for kernel
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* \author Norman Feske
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* \date 2013-04-05
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*/
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/*
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* Copyright (C) 2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _RPI__PIC_H_
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#define _RPI__PIC_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <base/stdint.h>
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/* core includes */
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#include <board.h>
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namespace Kernel
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{
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class Pic : Genode::Mmio
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{
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struct Irq_pending_basic : Register<0x0, 32>
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{
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struct Timer : Bitfield<0, 1> { };
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struct Gpu : Bitfield<8, 2> { };
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};
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struct Irq_pending_gpu_1 : Register<0x04, 32> { };
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struct Irq_pending_gpu_2 : Register<0x08, 32> { };
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struct Irq_enable_gpu_1 : Register<0x10, 32> { };
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struct Irq_enable_gpu_2 : Register<0x14, 32> { };
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struct Irq_enable_basic : Register<0x18, 32> { };
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struct Irq_disable_gpu_1 : Register<0x1c, 32> { };
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struct Irq_disable_gpu_2 : Register<0x20, 32> { };
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struct Irq_disable_basic : Register<0x24, 32> { };
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private:
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typedef Genode::uint32_t uint32_t;
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/**
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* Return true if specified interrupt is pending
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*/
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static bool _is_pending(unsigned i, uint32_t p1, uint32_t p2)
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{
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return i < 32 ? (p1 & (1 << i)) : (p2 & (1 << (i - 32)));
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}
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public:
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Pic() : Genode::Mmio(Genode::Board::IRQ_CONTROLLER_BASE) { }
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bool take_request(unsigned &irq)
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{
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/* read basic IRQ status mask */
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uint32_t const p = read<Irq_pending_basic>();
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/* read GPU IRQ status mask */
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uint32_t const p1 = read<Irq_pending_gpu_1>(),
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p2 = read<Irq_pending_gpu_2>();
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if (Irq_pending_basic::Timer::get(p)) {
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irq = 0;
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return true;
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}
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/* search for lowest set bit in pending masks */
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for (unsigned i = 0; i < 64; i++) {
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if (!_is_pending(i, p1, p2))
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continue;
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irq = Genode::Board_base::GPU_IRQ_BASE + i;
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return true;
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}
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return false;
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}
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void finish_request() { }
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void unmask() { PDBG("not implemented"); }
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void mask() { PDBG("not implemented"); }
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void unmask(unsigned const i)
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{
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if (i < 8)
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write<Irq_enable_basic>(1 << i);
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else if (i < 32 + 8) {
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write<Irq_enable_gpu_1>(1 << (i - 8));
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write<Irq_enable_basic>(1 << 8);
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} else {
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write<Irq_enable_gpu_2>(1 << (i - 8 - 32));
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write<Irq_enable_basic>(1 << 9);
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}
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}
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void mask(unsigned const i)
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{
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if (i < 8)
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write<Irq_disable_basic>(1 << i);
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else if (i < 32 + 8)
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write<Irq_disable_gpu_1>(1 << (i - 8));
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else
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write<Irq_disable_gpu_2>(1 << (i - 8 - 32));
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}
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};
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}
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#endif /* _RPI__PIC_H_ */
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