1668983efa
This commit adds rocket core on the Zynq FPGA support to base HW. It also takes advantage of the new timer infrastructure introduced with the privileged 1.8 and adds improved TLB flush support. fixes #1880
448 lines
8.3 KiB
ArmAsm
448 lines
8.3 KiB
ArmAsm
/*
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* \brief Transition between kernel/userland
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* \author Sebastian Sumpf
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* \author Mark Vels
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* \date 2015-06-22
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*/
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/*
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* Copyright (C) 2015-2016 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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.set USER_MODE, 0
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.set SUPERVISOR_MODE, 1
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.set MACHINE_MODE, 3
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.set CALL_PUT_CHAR, 0x100
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.set CALL_SET_SYS_TIMER, 0x101
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.set CALL_IS_USER_MODE, 0x102
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.set CPU_IP, 0
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.set CPU_EXCEPTION, 8
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.set CPU_X1, 2*8
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.set CPU_SP, 3*8
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.set CPU_SASID, 33*8
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.set CPU_SPTBR, 34*8
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# From encoding.h (riscv-opcode)
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.set MIP_MTIP, 0x00000020
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.set MIP_SSIP, 0x00000002
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.set MIP_HSIP, 0x00000004
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.set MIP_MSIP, 0x00000008
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.set MIP_STIP, 0x00000020
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.set MIP_HTIP, 0x00000040
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.set MIP_MTIP, 0x00000080
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.set MSTATUS_IE, 0x00000001
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.set MSTATUS_PRV, 0x00000006
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.set MSTATUS_IE1, 0x00000008
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.set MSTATUS_PRV1, 0x00000030
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.set MSTATUS_IE2, 0x00000040
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.set MSTATUS_PRV2, 0x00000180
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.set MSTATUS_IE3, 0x00000200
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.set MSTATUS_PRV3, 0x00000C00
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.set MSTATUS_FS, 0x00003000
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.set MSTATUS_XS, 0x0000C000
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.set MSTATUS_MPRV, 0x00010000
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.set MSTATUS_VM, 0x003E0000
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.set MSTATUS64_SD, 0x8000000000000000
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.set TRAP_ECALL_FROM_USER, 8
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.set TRAP_ECALL_FROM_SUPERVISOR, 9
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.set TRAP_ECALL_FROM_HYPERVISOR, 10
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.set TRAP_ECALL_FROM_MACHINE, 11
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.set TRAP_INTERRUPT_BITNR, 63
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.set IRQ_SOFT, 0x0
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.set IRQ_TIMER, 0x1
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.set IRQ_HOST, 0x2
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.set IRQ_COP, 0x3
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.macro _save_scratch_registers mode
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.if \mode == USER_MODE
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csrrw sp, mscratch, sp
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.endif
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addi sp, sp, -24
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sd t0, 0(sp)
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sd t1, 8(sp)
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sd t2, 16(sp)
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.endm
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.macro _restore_scratch_registers mode
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ld t0, 0(sp)
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ld t1, 8(sp)
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ld t2, 16(sp)
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addi sp, sp, 24
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.if \mode == USER_MODE
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csrrw sp, mscratch, sp
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.endif
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.endm
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.macro _handle_trap mode
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csrr t0, mcause
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# If IRQ bit not setup, goto trap handler.
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# If an interrupt has occurred, the MSB will be set and
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# hence mcause will be negative
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#
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bgez t0, 11f
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# The bit was not set so we're handling an interrupt
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# Valid interrupts are :
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# - Software IRQ - 0
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# - Timer IRQ - 1
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# - HOST HTIF - 2
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# - COP - 3
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#
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sll t0, t0, 1 # discard MSB
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# If interrupt source is IRQ TIMER ....
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li t1, IRQ_TIMER * 2
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bne t0, t1, 2f
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# Forward handling of timer IRQ to SUPERVISOR
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li t0, MIP_MTIP
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csrc mip, t0
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csrc mie, t0
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li t1, MIP_STIP
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csrs mip, t1
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# If irq from supervisor and MSTATUS.IE1 is not set,
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# then bail out using 'eret'
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#
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.if \mode == SUPERVISOR_MODE
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csrr t1, mstatus
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and t0, t1, MSTATUS_IE1
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bne zero, t0, 1f
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# So, IE1 is not set.
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_restore_scratch_registers \mode
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eret
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.endif
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1:
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# should cause a interrupt trap in supervisor mode
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_restore_scratch_registers \mode
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mrts
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2:
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# If interrupt source is IRQ HOST ....
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li t1, IRQ_HOST * 2
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bne t0, t1, 9f
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3:
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# Empty mfromhost
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li t0, 0
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csrrw t0, mfromhost, t0
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bne zero,t0, 3b
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j 9f
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# Future implementation check for more interrupt sources
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# to handle here.....
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9:
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#******** IRQ OUT *********
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_restore_scratch_registers \mode
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eret
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11:
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# Handle trap
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# check if ecall (8..11):
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# 8 : Environment call from U-mode
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# 9 : Environment call from S-mode
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# 10 : Environment call from H-mode
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# 11 : Environment call from M-mode
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#
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# If not, jump to end of macro.
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#
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li t1, TRAP_ECALL_FROM_USER
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bltu t0, t1, 19f
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li t1, TRAP_ECALL_FROM_MACHINE
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bgt t0, t1, 19f
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# Switch on ecall number
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li t1, CALL_PUT_CHAR
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beq t1, a0, 12f
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li t1, CALL_SET_SYS_TIMER
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beq t1, a0, 13f
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li t1, CALL_IS_USER_MODE
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beq t1, a0, 14f
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# else, unknown ecall number
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.if \mode == USER_MODE
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# Assume that Genode (supervisor trap handler)
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# knows what to do then.
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_restore_scratch_registers \mode
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mrts
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.endif
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j 15f
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12:
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# output character but first wait until mtohost reads 0 atomically
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# to make sure any previous character is gone..
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csrr t1, mtohost
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bne zero, t1, 12b
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csrw mtohost, a1
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j 15f
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13:
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# Only allow timer fiddling from supervisor mode
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.if \mode == SUPERVISOR_MODE
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# Clear any pending STIP
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li t0, MIP_STIP
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csrc mip, t0
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# Set system timer
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csrw mtimecmp, a1
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# enable timer interrupt in M-mode
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li t0, MIP_MTIP
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csrrs t0, mie, t0
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.endif
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j 15f
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14:
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mv a0, x0
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.if \mode == USER_MODE
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li a0, 1
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.endif
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j 15f
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15:
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#******* ECALL OUT *********
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# Empty mfromhost
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li t0, 0
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csrrw t0, mfromhost, t0
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bne zero,t0, 14b
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# advance epc
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csrr t0, mepc
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addi t0, t0, 4
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csrw mepc, t0
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_restore_scratch_registers \mode
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eret
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19:
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.endm
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.section .text
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##
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# Page aligned base of mode transition code.
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#
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# This position independent code switches between a kernel context and a
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# user context and thereby between their address spaces. Due to the latter
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# it must be mapped executable to the same region in every address space.
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# To enable such switching, the kernel context must be stored within this
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# region, thus one should map it solely accessable for privileged modes.
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#
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.p2align 8
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.global _machine_begin
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_machine_begin:
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# 0x100 user mode
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j user_trap
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.space 0x3c
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# 0x140 supervisor
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j supervisor_trap
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.space 0x3c
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# 0x180 hypervisor
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1: j 1b
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.space 0x3c
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# 0x1c0 machine
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j machine_trap
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.space 0x38
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# 0x1fc non-maksable interrupt
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1: j 1b
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user_trap:
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_save_scratch_registers USER_MODE
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_handle_trap USER_MODE
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_restore_scratch_registers USER_MODE
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mrts
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supervisor_trap:
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_save_scratch_registers SUPERVISOR_MODE
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_handle_trap SUPERVISOR_MODE
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j fault
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machine_trap:
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_save_scratch_registers MACHINE_MODE
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_handle_trap MACHINE_MODE
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j fault
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fault:j fault # TODO: handle trap from supervisor or machine mode
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.global _machine_end
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_machine_end:
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.p2align 12
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.global _mt_begin
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_mt_begin:
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# 0x100 user mode
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j _mt_kernel_entry_pic
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.space 0x3c
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# 0x140 supervisor
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1: j 1b
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.space 0x3c
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# 0x180 hypervisor
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1: j 1b
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.space 0x3c
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# 0x1c0 machine
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1: j 1b
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.space 0x38
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# 0x1fc non-maksable interrupt
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1: j 1b
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/* space for a client context-pointer per CPU */
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.p2align 3
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.global _mt_client_context_ptr
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_mt_client_context_ptr:
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.space 8
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/* space for a copy of the kernel context */
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.global _mt_master_context_begin
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_mt_master_context_begin:
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/* space must be at least as large as 'Context' */
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.space 35*8
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.global _mt_master_context_end
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_mt_master_context_end:
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.global _mt_kernel_entry_pic
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_mt_kernel_entry_pic:
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# master context
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csrrw x31, sscratch, x31
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addi x31, x31, 8
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# save x29, x30 in master
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sd x29, CPU_X1 + 8 * 28(x31)
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sd x30, CPU_X1 + 8 * 29(x31)
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# load kernel page table
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ld x29, CPU_SASID(x31)
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ld x30, CPU_SPTBR(x31)
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csrw sasid, x29
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csrw sptbr, x30
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#
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# FIXME
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# A TLB flush. Might be necessary to remove this in the near future again
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# because on real hardware we currently get problems without.
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#
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sfence.vm x0
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# save x29 - x31 in user context
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mv x29, x31
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addi x29, x29, -8
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ld x29, (x29)
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.irp reg,29,30
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ld x30, CPU_X1 + 8 * (\reg - 1)(x31)
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sd x30, CPU_X1 + 8 * (\reg - 1)(x29)
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.endr
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csrr x30, sscratch /* x31 */
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sd x30, CPU_X1 + 8 * 30(x29)
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# save x1 - x28
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.irp reg,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28
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sd x\reg, CPU_X1 + 8 * (\reg - 1)(x29)
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.endr
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# trap reason
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csrr x30, scause
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sd x30, CPU_EXCEPTION(x29)
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# ip
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csrr x30, sepc
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sd x30, CPU_IP(x29)
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# load kernel stack and ip
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ld sp, CPU_SP(x31)
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ld x30, CPU_IP(x31)
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# restore scratch
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addi x31, x31, -8
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csrw sscratch, x31
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jalr x30
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.global _mt_user_entry_pic
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_mt_user_entry_pic:
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# client context pointer
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csrr x30, sscratch
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ld x30, (x30)
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# set return IP
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ld x31, CPU_IP(x30)
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csrw sepc, x31
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# restore x1-x28
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.irp reg,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28
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ld x\reg, CPU_X1 + 8 * (\reg - 1)(x30)
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.endr
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# save x29, x30, x31 to master context
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csrr x29, sscratch
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addi x29, x29, 8 # master context
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.irp reg,29,30,31
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ld x31, CPU_X1 + 8 * (\reg - 1)(x30)
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sd x31, CPU_X1 + 8 * (\reg - 1)(x29)
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.endr
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# switch page table
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ld x31, CPU_SASID(x30)
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ld x30, CPU_SPTBR(x30)
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csrw sasid, x31
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csrw sptbr, x30
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#
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# FIXME
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# A TLB flush. Might be necessary to remove this in the near future again
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# because on real hardware we currently get problems without.
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#
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sfence.vm x0
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# restore x29 - x31 from master context
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.irp reg,31,30,29
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ld x\reg, CPU_X1 + 8 * (\reg - 1)(x29)
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.endr
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eret
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# end of the mode transition code
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.global _mt_end
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_mt_end:
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