78 lines
1.6 KiB
C++
78 lines
1.6 KiB
C++
/*
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* \brief Driver for the Versatile Express A9X4 board
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* \author Martin stein
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* \date 2011-11-03
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*/
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/*
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* Copyright (C) 2011-2012 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _INCLUDE__DRIVERS__BOARD_H_
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#define _INCLUDE__DRIVERS__BOARD_H_
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namespace Genode
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{
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/**
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* Driver for the Versatile Express A9X4 board
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*
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* Implies the uATX motherboard and the CoreTile Express A9X4 daughterboard
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*/
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struct Board
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{
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enum
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{
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/* static memory bus */
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SMB_CS2_BASE = 0x48000000,
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SMB_CS7_BASE = 0x10000000,
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SMB_CS7_SIZE = 0x20000,
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SMB_CS0_TO_CS6_BASE = 0x40000000,
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SMB_CS0_TO_CS6_SIZE = 0x20000000,
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/* UART */
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PL011_0_MMIO_BASE = SMB_CS7_BASE + 0x9000,
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PL011_0_MMIO_SIZE = 0x1000,
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PL011_0_CLOCK = 24*1000*1000,
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PL011_0_IRQ = 5,
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/* timer/counter */
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SP804_0_1_MMIO_BASE = SMB_CS7_BASE + 0x11000,
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SP804_0_1_MMIO_SIZE = 0x1000,
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SP804_0_1_CLOCK = 1000*1000,
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SP804_0_1_IRQ = 34,
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/* clocks */
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TCREF_CLOCK = 66670*1000,
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/* TrustZone Address Space Controller */
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TZASC_MMIO_BASE = 0x100ec000,
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TZASC_MMIO_SIZE = 0x1000,
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/* TrustZone Protection Controller */
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TZPC_MMIO_BASE = 0x100e6000,
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TZPC_MMIO_SIZE = 0x1000,
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/* CPU */
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CORTEX_A9_PRIVATE_MEM_BASE = 0x1e000000,
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CORTEX_A9_PRIVATE_MEM_SIZE = 0x2000,
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CORTEX_A9_CLOCK = TCREF_CLOCK,
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/* RAM */
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LOCAL_DDR2_BASE = 0x60000000,
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LOCAL_DDR2_SIZE = 0x40000000,
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/* SRAM */
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SRAM_BASE = SMB_CS2_BASE,
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SRAM_SIZE = 0x01ffffff,
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SECURITY_EXTENSION = 1,
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};
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};
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}
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#endif /* _INCLUDE__DRIVERS__BOARD_H_ */
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