114 lines
2.6 KiB
C++
114 lines
2.6 KiB
C++
/*
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* \brief TLB driver for core
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* \author Martin Stein
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* \date 2012-02-22
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*/
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/*
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* Copyright (C) 2012-2013 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _TLB__ARM_V6_H_
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#define _TLB__ARM_V6_H_
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/* core includes */
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#include <tlb/arm.h>
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namespace Arm_v6
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{
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using namespace Genode;
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/**
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* First level translation table
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*/
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class Section_table : public Arm::Section_table
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{
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public:
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/**
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* Link to second level translation-table
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*/
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struct Page_table_descriptor : Arm::Section_table::Page_table_descriptor
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{
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/**
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* Compose descriptor value
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*/
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static access_t create(Arm::Page_table * const pt,
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Section_table *)
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{
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return Arm::Section_table::Page_table_descriptor::create(pt);
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}
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};
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/**
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* Section translation descriptor
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*/
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struct Section : Arm::Section_table::Section
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{
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struct P : Bitfield<9, 1> { }; /* enable ECC */
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/**
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* Compose descriptor value
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*/
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static access_t create(Page_flags const &flags,
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addr_t const pa, Section_table *)
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{
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return Arm::Section_table::Section::create(flags, pa) |
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P::bits(0);
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}
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};
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/**
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* Insert one atomic translation into this table
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*
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* For details see 'Arm::Section_table::insert_translation'
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*/
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size_t
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insert_translation(addr_t const vo, addr_t const pa,
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size_t const size_log2,
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Page_flags const &flags,
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void * const extra_space = 0) {
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return Arm::Section_table::
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insert_translation<Section_table>(vo, pa, size_log2, flags,
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this, extra_space); }
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/**
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* Insert translations for given area, do not permit displacement
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*
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* \param vo virtual offset within this table
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* \param s area size
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* \param io_mem wether the area maps MMIO
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*/
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void map_core_area(addr_t vo, size_t s, bool const io_mem) {
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Arm::Section_table::map_core_area<Section_table>(vo, s, io_mem,
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this); }
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};
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}
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template <typename T>
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static typename T::access_t
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Arm::memory_region_attr(Page_flags const &flags)
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{
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typedef typename T::Tex Tex;
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typedef typename T::C C;
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typedef typename T::B B;
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/*
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* FIXME: upgrade to write-back & write-allocate when !d & c
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*/
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if(flags.device)
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return 0;
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if(flags.cacheable)
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return Tex::bits(5) | C::bits(0) | B::bits(1);
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return Tex::bits(6) | C::bits(1) | B::bits(0);
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}
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#endif /* _TLB__ARM_V6_H_ */
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