6106e64aac
This commit moves the headers residing in `repos/base/include/spec/*/drivers` to `repos/base/include/drivers/defs` or repos/base/include/drivers/uart` respectively. The first one contains definitions about board-specific MMIO iand RAM addresses, or IRQ lines. While the latter contains device driver code for UART devices. Those definitions are used by driver implementations in `repos/base-hw`, `repos/os`, and `repos/dde-linux`, which now need to include them more explicitely. This work is a step in the direction of reducing 'SPEC' identifiers overall. Ref #2403
95 lines
2.1 KiB
C++
95 lines
2.1 KiB
C++
/*
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* \brief Clock control module register description
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* \author Nikolay Golikov <nik@ksyslabs.org>
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* \author Stefan Kalkowski <stefan.kalkowski@genode-labs.com>
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* \date 2013-04-29
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*/
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/*
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* Copyright (C) 2013-2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _DRIVERS__PLATFORM__SPEC__IMX53__CCM_H_
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#define _DRIVERS__PLATFORM__SPEC__IMX53__CCM_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <drivers/defs/imx53.h>
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#include <base/attached_io_mem_dataspace.h>
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class Ccm : public Genode::Attached_io_mem_dataspace,
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Genode::Mmio
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{
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private:
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/**
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* Control divider register
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*/
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struct Ccdr : Register<0x4, 32>
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{
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struct Ipu_hs_mask : Bitfield <21, 1> { };
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};
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/**
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* Serial Clock Multiplexer Register 2
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*/
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struct Cscmr2 : Register<0x20, 32> {};
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/**
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* D1 Clock Divider Register
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*/
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struct Cdcdr : Register<0x30, 32> {};
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/**
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* Low power control register
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*/
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struct Clpcr : Register<0x54, 32>
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{
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struct Bypass_ipu_hs : Bitfield<18, 1> { };
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};
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struct Ccgr1 : Register<0x6c, 32>
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{
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struct I2c_1 : Bitfield<18, 2> { };
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struct I2c_2 : Bitfield<20, 2> { };
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struct I2c_3 : Bitfield<22, 2> { };
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};
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struct Ccgr5 : Register<0x7c, 32>
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{
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struct Ipu : Bitfield<10, 2> { };
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};
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public:
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Ccm(Genode::Env &env)
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: Genode::Attached_io_mem_dataspace(env, Imx53::CCM_BASE,
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Imx53::CCM_SIZE),
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Genode::Mmio((Genode::addr_t)local_addr<void>()) { }
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void i2c_1_enable(void) { write<Ccgr1::I2c_1>(3); }
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void i2c_2_enable(void) { write<Ccgr1::I2c_2>(3); }
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void i2c_3_enable(void) { write<Ccgr1::I2c_3>(3); }
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void ipu_clk_enable(void)
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{
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write<Ccgr5::Ipu>(3);
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write<Ccdr::Ipu_hs_mask>(0);
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write<Clpcr::Bypass_ipu_hs>(0);
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write<Cscmr2>(0xa2b32f0b);
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write<Cdcdr>(0x14370092);
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}
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void ipu_clk_disable(void)
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{
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write<Ccgr5::Ipu>(0);
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write<Ccdr::Ipu_hs_mask>(1);
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write<Clpcr::Bypass_ipu_hs>(1);
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}
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};
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#endif /* _DRIVERS__PLATFORM__SPEC__IMX53__CCM_H_ */
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