150 lines
3.5 KiB
C++
150 lines
3.5 KiB
C++
/*
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* \brief Timer driver for core
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* \author Adrian-Ken Rueegsegger
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* \author Reto Buerki
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* \date 2015-02-06
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#ifndef _CORE__INCLUDE__SPEC__X86_64__TIMER_H_
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#define _CORE__INCLUDE__SPEC__X86_64__TIMER_H_
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/* base-hw includes */
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#include <kernel/types.h>
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/* Genode includes */
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#include <util/mmio.h>
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#include <base/stdint.h>
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/* core includes */
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#include <port_io.h>
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#include <board.h>
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namespace Genode { class Timer; }
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/**
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* LAPIC-based timer driver for core
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*/
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class Genode::Timer : public Mmio
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{
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private:
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using time_t = Kernel::time_t;
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enum {
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/* PIT constants */
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PIT_TICK_RATE = 1193182ul,
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PIT_SLEEP_MS = 50,
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PIT_SLEEP_TICS = (PIT_TICK_RATE / 1000) * PIT_SLEEP_MS,
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PIT_CH0_DATA = 0x40,
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PIT_CH2_DATA = 0x42,
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PIT_CH2_GATE = 0x61,
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PIT_MODE = 0x43,
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};
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/* Timer registers */
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struct Tmr_lvt : Register<0x320, 32>
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{
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struct Vector : Bitfield<0, 8> { };
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struct Delivery : Bitfield<8, 3> { };
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struct Mask : Bitfield<16, 1> { };
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struct Timer_mode : Bitfield<17, 2> { };
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};
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struct Tmr_initial : Register <0x380, 32> { };
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struct Tmr_current : Register <0x390, 32> { };
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struct Divide_configuration : Register <0x03e0, 32>
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{
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struct Divide_value_0_2 : Bitfield<0, 2> { };
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struct Divide_value_2_1 : Bitfield<3, 1> { };
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struct Divide_value :
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Bitset_2<Divide_value_0_2, Divide_value_2_1>
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{
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enum { MAX = 6 };
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};
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};
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uint32_t _tics_per_ms = 0;
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/* Measure LAPIC timer frequency using PIT channel 2 */
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uint32_t _pit_calc_timer_freq(void)
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{
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uint32_t t_start, t_end;
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/* Set channel gate high and disable speaker */
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outb(PIT_CH2_GATE, (inb(0x61) & ~0x02) | 0x01);
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/* Set timer counter (mode 0, binary count) */
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outb(PIT_MODE, 0xb0);
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outb(PIT_CH2_DATA, PIT_SLEEP_TICS & 0xff);
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outb(PIT_CH2_DATA, PIT_SLEEP_TICS >> 8);
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write<Tmr_initial>(~0U);
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t_start = read<Tmr_current>();
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while ((inb(PIT_CH2_GATE) & 0x20) == 0)
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{
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asm volatile("pause" : : : "memory");
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}
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t_end = read<Tmr_current>();
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write<Tmr_initial>(0);
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return (t_start - t_end) / PIT_SLEEP_MS;
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}
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public:
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Timer() : Mmio(Board::MMIO_LAPIC_BASE)
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{
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write<Divide_configuration::Divide_value>(
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Divide_configuration::Divide_value::MAX);
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/* Enable LAPIC timer in one-shot mode */
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write<Tmr_lvt::Vector>(Board::TIMER_VECTOR_KERNEL);
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write<Tmr_lvt::Delivery>(0);
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write<Tmr_lvt::Mask>(0);
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write<Tmr_lvt::Timer_mode>(0);
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/* Calculate timer frequency */
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_tics_per_ms = _pit_calc_timer_freq();
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}
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/**
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* Disable PIT timer channel. This is necessary since BIOS sets up
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* channel 0 to fire periodically.
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*/
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static void disable_pit()
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{
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outb(PIT_MODE, 0x30);
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outb(PIT_CH0_DATA, 0);
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outb(PIT_CH0_DATA, 0);
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}
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static unsigned interrupt_id(unsigned const) {
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return Board::TIMER_VECTOR_KERNEL; }
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void start_one_shot(time_t const tics, unsigned const) {
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write<Tmr_initial>(tics); }
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time_t tics_to_us(time_t const tics) const {
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return (tics / _tics_per_ms) * 1000; }
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time_t us_to_tics(time_t const us) const {
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return (us / 1000) * _tics_per_ms; }
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time_t max_value() { return (Tmr_initial::access_t)~0; }
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time_t value(unsigned const) { return read<Tmr_current>(); }
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};
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namespace Kernel { class Timer : public Genode::Timer { }; }
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#endif /* _CORE__INCLUDE__SPEC__X86_64__TIMER_H_ */
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