82 lines
1.5 KiB
C++
82 lines
1.5 KiB
C++
/*
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* \brief Programmable interrupt controller for core
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* \author Adrian-Ken Rueegsegger
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* \author Reto Buerki
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* \date 2015-02-17
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*/
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/*
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* Copyright (C) 2015 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU General Public License version 2.
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*/
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#include <port_io.h>
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#include "pic.h"
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using namespace Genode;
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enum {
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PIC_CMD_MASTER = 0x20,
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PIC_CMD_SLAVE = 0xa0,
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PIC_DATA_MASTER = 0x21,
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PIC_DATA_SLAVE = 0xa1,
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};
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Pic::Pic() : Mmio(Board::MMIO_LAPIC_BASE)
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{
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/* Start initialization sequence in cascade mode */
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outb(PIC_CMD_MASTER, 0x11);
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outb(PIC_CMD_SLAVE, 0x11);
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/* ICW2: Master PIC vector offset (32) */
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outb(PIC_DATA_MASTER, 0x20);
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/* ICW2: Slave PIC vector offset (40) */
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outb(PIC_DATA_SLAVE, 0x28);
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/* ICW3: Tell Master PIC that there is a slave PIC at IRQ2 */
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outb(PIC_DATA_MASTER, 4);
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/* ICW3: Tell Slave PIC its cascade identity */
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outb(PIC_DATA_SLAVE, 2);
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/* ICW4: Enable 8086 mode */
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outb(PIC_DATA_MASTER, 0x01);
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outb(PIC_DATA_SLAVE, 0x01);
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/* Disable legacy pic */
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outb(PIC_DATA_SLAVE, 0xff);
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outb(PIC_DATA_MASTER, 0xff);
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/* Set bit 8 of the APIC spurious vector register (SVR) */
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write<Svr::APIC_enable>(1);
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}
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bool Pic::take_request(unsigned &irq)
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{
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irq = get_lowest_bit();
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if (!irq) {
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return false;
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}
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irq -= 1;
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return true;
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}
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void Pic::finish_request()
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{
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write<EOI>(0);
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}
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void Pic::unmask(unsigned const i, unsigned)
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{
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_ioapic.toggle_mask(i, false);
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}
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void Pic::mask(unsigned const i)
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{
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_ioapic.toggle_mask(i, true);
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}
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