198019edca
This commit introduces a experimental 3D driver for Intel Gen8 HD graphics devices as well as the corresponding Gpu session. Fixes #2507.
203 lines
4.9 KiB
C++
203 lines
4.9 KiB
C++
/*
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* \brief Broadwell MI commands
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* \author Josef Soentgen
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* \date 2017-03-15
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*/
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/*
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* Copyright (C) 2017 Genode Labs GmbH
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*
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* This file is part of the Genode OS framework, which is distributed
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* under the terms of the GNU Affero General Public License version 3.
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*/
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#ifndef _COMMANDS_H_
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#define _COMMANDS_H_
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/* Genode includes */
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#include <util/mmio.h>
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#include <util/string.h>
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/* local includes */
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#include <types.h>
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namespace Igd {
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struct Cmd_header;
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struct Mi_noop;
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struct Mi_user_interrupt;
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struct Mi_batch_buffer_start;
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struct Pipe_control;
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void cmd_dump(uint32_t cmd, uint32_t index = 0);
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}
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/*
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* IHD-OS-BDW-Vol 6-11.15 p. 2
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*/
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struct Igd::Cmd_header : Genode::Register<32>
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{
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struct Cmd_type : Bitfield<29, 3>
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{
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enum {
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MI_COMMAND = 0b000,
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MI_BCS = 0b010,
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MI_RCS = 0b011,
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};
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};
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struct Cmd_subtype : Bitfield<27, 2> { };
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struct Cmd_opcode : Bitfield<24, 3> { };
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/*
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* Actually bit 23:x seems to be the sub-opcode but opcodes
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* include bit 23 (see p. 5).
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*/
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struct Mi_cmd_opcode : Bitfield<23, 6>
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{
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enum {
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MI_NOOP = 0x00,
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MI_USER_INTERRUPT = 0x02,
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MI_WAIT_FOR_EVENT = 0x03,
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MI_FLUSH = 0x04,
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MI_REPORT_HEAD = 0x07,
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MI_ARB_ON_OFF = 0x08,
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MI_BATCH_BUFFER_END = 0x0A,
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MI_SUSPEND_FLUSH = 0x0B,
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MI_SET_APPID = 0x0E,
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MI_OVERLAY_FLIP = 0x11,
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MI_LOAD_SCAN_LINES_INCL = 0x12,
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MI_DISPLAY_FLIP = 0x14,
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MI_DISPLAY_FLIP_I915 = 0x14,
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MI_SEMAPHORE_MBOX = 0x16,
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MI_SET_CONTEXT = 0x18,
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MI_SEMAPHORE_SIGNAL = 0x1b,
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MI_SEMAPHORE_WAIT = 0x1c,
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MI_STORE_DWORD_IMM = 0x20,
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MI_STORE_DWORD_INDEX = 0x21,
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MI_LOAD_REGISTER_IMM = 0x22,
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MI_STORE_REGISTER_MEM = 0x24,
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MI_FLUSH_DW = 0x26,
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MI_LOAD_REGISTER_MEM = 0x29,
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MI_BATCH_BUFFER = 0x30,
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MI_BATCH_BUFFER_START = 0x31,
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};
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};
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typename Cmd_header::access_t value;
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Cmd_header() : value(0) { }
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Cmd_header(Igd::uint32_t value) : value(value) { }
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};
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/*
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* IHD-OS-BDW-Vol 2a-11.15 p. 870
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*/
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struct Igd::Mi_noop : Cmd_header
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{
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Mi_noop()
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{
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Cmd_header::Cmd_type::set(Cmd_header::value,
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Cmd_header::Cmd_type::MI_COMMAND);
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Cmd_header::Mi_cmd_opcode::set(Cmd_header::value,
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Cmd_header::Mi_cmd_opcode::MI_NOOP);
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}
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};
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/*
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* IHD-OS-BDW-Vol 2a-11.15 p. 948 ff.
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*/
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struct Igd::Mi_user_interrupt : Cmd_header
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{
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Mi_user_interrupt()
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{
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Cmd_header::Cmd_type::set(Cmd_header::value,
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Cmd_header::Cmd_type::MI_COMMAND);
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Cmd_header::Mi_cmd_opcode::set(Cmd_header::value,
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Cmd_header::Mi_cmd_opcode::MI_USER_INTERRUPT);
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}
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};
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/*
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* IHD-OS-BDW-Vol 2a-11.15 p. 793 ff.
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*/
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struct Igd::Mi_batch_buffer_start : Cmd_header
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{
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struct Address_space_indicator : Bitfield<8, 1>
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{
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enum { GTT = 0b0, PPGTT = 0b1, };
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};
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struct Dword_length : Bitfield<0, 8> { };
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Mi_batch_buffer_start()
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{
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Cmd_header::Cmd_type::set(Cmd_header::value,
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Cmd_header::Cmd_type::MI_COMMAND);
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Cmd_header::Mi_cmd_opcode::set(Cmd_header::value,
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Cmd_header::Mi_cmd_opcode::MI_BATCH_BUFFER_START);
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Address_space_indicator::set(Cmd_header::value, Address_space_indicator::PPGTT);
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Dword_length::set(Cmd_header::value, 1);
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}
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};
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/*
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* IHD-OS-BDW-Vol 2a-11.15 p. 983 ff.
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*/
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struct Igd::Pipe_control : Cmd_header
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{
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struct Dword_length : Bitfield<0, 8> { };
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enum {
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GFX_PIPE_LINE = 0b11,
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PIPE_CONTROL = 0b10,
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};
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enum {
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FLUSH_L3 = (1 << 27),
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GLOBAL_GTT_IVB = (1 << 24),
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MMIO_WRITE = (1 << 23),
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STORE_DATA_INDEX = (1 << 21),
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CS_STALL = (1 << 20),
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TLB_INVALIDATE = (1 << 18),
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MEDIA_STATE_CLEAR = (1 << 16),
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QW_WRITE = (1 << 14),
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POST_SYNC_OP_MASK = (3 << 14),
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DEPTH_STALL = (1 << 13),
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WRITE_FLUSH = (1 << 12),
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RENDER_TARGET_CACHE_FLUSH = (1 << 12),
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INSTRUCTION_CACHE_INVALIDATE = (1 << 11),
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TEXTURE_CACHE_INVALIDATE = (1 << 10),
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INDIRECT_STATE_DISABLE = (1 << 9),
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NOTIFY = (1 << 8),
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FLUSH_ENABLE = (1 << 7),
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DC_FLUSH_ENABLE = (1 << 5),
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VF_CACHE_INVALIDATE = (1 << 4),
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CONST_CACHE_INVALIDATE = (1 << 3),
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STATE_CACHE_INVALIDATE = (1 << 2),
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STALL_AT_SCOREBOARD = (1 << 1),
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DEPTH_CACHE_FLUSH = (1 << 0),
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};
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Pipe_control(Genode::uint8_t length)
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{
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Cmd_header::Cmd_type::set(Cmd_header::value,
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Cmd_header::Cmd_type::MI_RCS);
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Cmd_header::Cmd_subtype::set(Cmd_header::value, GFX_PIPE_LINE);
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Cmd_header::Cmd_opcode::set(Cmd_header::value, PIPE_CONTROL);
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Dword_length::set(Cmd_header::value, (length-2));
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}
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};
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#endif /* _COMMANDS_H_ */
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